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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 | /* * Copyright (c) 2017 Linaro Limited * Copyright (c) 2023 Google Inc * * SPDX-License-Identifier: Apache-2.0 */ #include <string.h> #include <zephyr/device.h> #include <zephyr/drivers/flash.h> #include <zephyr/init.h> #include <zephyr/kernel.h> #include <zephyr/logging/log.h> #include <zephyr/sys/barrier.h> #include <soc.h> #include "flash_stm32.h" LOG_MODULE_REGISTER(flash_stm32f4x, CONFIG_FLASH_LOG_LEVEL); bool flash_stm32_valid_range(const struct device *dev, off_t offset, uint32_t len, bool write) { ARG_UNUSED(write); #if (FLASH_SECTOR_TOTAL == 12) && defined(FLASH_OPTCR_DB1M) FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); /* * RM0090, table 7.1: STM32F42xxx, STM32F43xxx */ if (regs->OPTCR & FLASH_OPTCR_DB1M) { /* Device configured in Dual Bank, but not supported for now */ return false; } #endif return flash_stm32_range_exists(dev, offset, len); } static inline void flush_cache(FLASH_TypeDef *regs) { if (regs->ACR & FLASH_ACR_DCEN) { regs->ACR &= ~FLASH_ACR_DCEN; /* Datasheet: DCRST: Data cache reset * This bit can be written only when the data cache is disabled */ regs->ACR |= FLASH_ACR_DCRST; regs->ACR &= ~FLASH_ACR_DCRST; regs->ACR |= FLASH_ACR_DCEN; } if (regs->ACR & FLASH_ACR_ICEN) { regs->ACR &= ~FLASH_ACR_ICEN; /* Datasheet: ICRST: Instruction cache reset : * This bit can be written only when the instruction cache * is disabled */ regs->ACR |= FLASH_ACR_ICRST; regs->ACR &= ~FLASH_ACR_ICRST; regs->ACR |= FLASH_ACR_ICEN; } } static int write_byte(const struct device *dev, off_t offset, uint8_t val) { FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); #if defined(FLASH_OPTCR_DB1M) bool dcache_enabled = false; #endif /* FLASH_OPTCR_DB*/ uint32_t tmp; int rc; /* if the control register is locked, do not fail silently */ if (regs->CR & FLASH_CR_LOCK) { return -EIO; } rc = flash_stm32_wait_flash_idle(dev); if (rc < 0) { return rc; } #if defined(FLASH_OPTCR_DB1M) /* * Disable the data cache to avoid the silicon errata ES0206 Rev 16 2.2.12: * "Data cache might be corrupted during Flash memory read-while-write operation" */ if (regs->ACR & FLASH_ACR_DCEN) { dcache_enabled = true; regs->ACR &= (~FLASH_ACR_DCEN); } #endif /* FLASH_OPTCR_DB1M */ regs->CR &= CR_PSIZE_MASK; regs->CR |= FLASH_PSIZE_BYTE; regs->CR |= FLASH_CR_PG; /* flush the register write */ tmp = regs->CR; *((uint8_t *) offset + CONFIG_FLASH_BASE_ADDRESS) = val; rc = flash_stm32_wait_flash_idle(dev); regs->CR &= (~FLASH_CR_PG); #if defined(FLASH_OPTCR_DB1M) /* Reset/enable the data cache if previously enabled */ if (dcache_enabled) { regs->ACR |= FLASH_ACR_DCRST; regs->ACR &= (~FLASH_ACR_DCRST); regs->ACR |= FLASH_ACR_DCEN; } #endif /* FLASH_OPTCR_DB1M */ return rc; } static int erase_sector(const struct device *dev, uint32_t sector) { FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); uint32_t tmp; int rc; /* if the control register is locked, do not fail silently */ if (regs->CR & FLASH_CR_LOCK) { return -EIO; } rc = flash_stm32_wait_flash_idle(dev); if (rc < 0) { return rc; } /* * If an erase operation in Flash memory also concerns data * in the instruction cache, the user has to ensure that these data * are rewritten before they are accessed during code execution. */ flush_cache(regs); #if FLASH_SECTOR_TOTAL == 24 /* * RM0090, §3.9.8: STM32F42xxx, STM32F43xxx * RM0386, §3.7.5: STM32F469xx, STM32F479xx */ if (sector >= 12) { /* From sector 12, SNB is offset by 0b10000 */ sector += 4U; } #endif regs->CR &= ~FLASH_CR_SNB; regs->CR |= FLASH_CR_SER | (sector << 3); regs->CR |= FLASH_CR_STRT; /* flush the register write */ tmp = regs->CR; rc = flash_stm32_wait_flash_idle(dev); regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB); return rc; } int flash_stm32_block_erase_loop(const struct device *dev, unsigned int offset, unsigned int len) { struct flash_pages_info info; uint32_t start_sector, end_sector; uint32_t i; int rc = 0; rc = flash_get_page_info_by_offs(dev, offset, &info); if (rc) { return rc; } start_sector = info.index; rc = flash_get_page_info_by_offs(dev, offset + len - 1, &info); if (rc) { return rc; } end_sector = info.index; for (i = start_sector; i <= end_sector; i++) { rc = erase_sector(dev, i); if (rc < 0) { break; } } return rc; } int flash_stm32_write_range(const struct device *dev, unsigned int offset, const void *data, unsigned int len) { int i, rc = 0; for (i = 0; i < len; i++, offset++) { rc = write_byte(dev, offset, ((const uint8_t *) data)[i]); if (rc < 0) { return rc; } } return rc; } static __unused int write_optb(const struct device *dev, uint32_t mask, uint32_t value) { FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); int rc; if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { return -EIO; } if ((regs->OPTCR & mask) == value) { return 0; } rc = flash_stm32_wait_flash_idle(dev); if (rc < 0) { return rc; } regs->OPTCR = (regs->OPTCR & ~mask) | value; regs->OPTCR |= FLASH_OPTCR_OPTSTRT; /* Make sure previous write is completed. */ barrier_dsync_fence_full(); rc = flash_stm32_wait_flash_idle(dev); if (rc < 0) { return rc; } return 0; } #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT) int flash_stm32_update_wp_sectors(const struct device *dev, uint32_t changed_sectors, uint32_t protected_sectors) { changed_sectors <<= FLASH_OPTCR_nWRP_Pos; protected_sectors <<= FLASH_OPTCR_nWRP_Pos; if ((changed_sectors & FLASH_OPTCR_nWRP_Msk) != changed_sectors) { return -EINVAL; } /* Sector is protected when bit == 0. Flip protected_sectors bits */ protected_sectors = ~protected_sectors & changed_sectors; return write_optb(dev, changed_sectors, protected_sectors); } int flash_stm32_get_wp_sectors(const struct device *dev, uint32_t *protected_sectors) { FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); *protected_sectors = (~regs->OPTCR & FLASH_OPTCR_nWRP_Msk) >> FLASH_OPTCR_nWRP_Pos; return 0; } #endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */ #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION) int flash_stm32_update_rdp(const struct device *dev, bool enable, bool permanent) { FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); uint8_t current_level, target_level; current_level = (regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos; target_level = current_level; /* * 0xAA = RDP level 0 (no protection) * 0xCC = RDP level 2 (permanent protection) * others = RDP level 1 (protection active) */ switch (current_level) { case FLASH_STM32_RDP2: if (!enable || !permanent) { __ASSERT(false, "RDP level 2 is permanent and can't be " "changed!"); return -ENOTSUP; } break; case FLASH_STM32_RDP0: if (enable) { target_level = FLASH_STM32_RDP1; if (permanent) { #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW) target_level = FLASH_STM32_RDP2; #else __ASSERT(false, "Permanent readout protection (RDP " "level 0 -> 2) not allowed"); return -ENOTSUP; #endif } } break; default: /* FLASH_STM32_RDP1 */ if (enable && permanent) { #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW) target_level = FLASH_STM32_RDP2; #else __ASSERT(false, "Permanent readout protection (RDP " "level 1 -> 2) not allowed"); return -ENOTSUP; #endif } if (!enable) { #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW) target_level = FLASH_STM32_RDP0; #else __ASSERT(false, "Disabling readout protection (RDP " "level 1 -> 0) not allowed"); return -EACCES; #endif } } /* Update RDP level if needed */ if (current_level != target_level) { LOG_INF("RDP changed from 0x%02x to 0x%02x", current_level, target_level); write_optb(dev, FLASH_OPTCR_RDP_Msk, (uint32_t)target_level << FLASH_OPTCR_RDP_Pos); } return 0; } int flash_stm32_get_rdp(const struct device *dev, bool *enabled, bool *permanent) { FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); uint8_t current_level; current_level = (regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos; /* * 0xAA = RDP level 0 (no protection) * 0xCC = RDP level 2 (permanent protection) * others = RDP level 1 (protection active) */ switch (current_level) { case FLASH_STM32_RDP2: *enabled = true; *permanent = true; break; case FLASH_STM32_RDP0: *enabled = false; *permanent = false; break; default: /* FLASH_STM32_RDP1 */ *enabled = true; *permanent = false; } return 0; } #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */ /* * Different SoC flash layouts are specified in across various * reference manuals, but the flash layout for a given number of * sectors is consistent across these manuals, with one "gotcha". The * number of sectors is given by the HAL as FLASH_SECTOR_TOTAL. * * The only "gotcha" is that when there are 24 sectors, they are split * across 2 "banks" of 12 sectors each, with another set of small * sectors (16 KB) in the second bank occurring after the large ones * (128 KB) in the first. We could consider supporting this as two * devices to make the layout cleaner, but this will do for now. */ #ifndef FLASH_SECTOR_TOTAL #error "Unknown flash layout" #else /* defined(FLASH_SECTOR_TOTAL) */ #if FLASH_SECTOR_TOTAL == 5 static const struct flash_pages_layout stm32f4_flash_layout[] = { /* RM0401, table 5: STM32F410Tx, STM32F410Cx, STM32F410Rx */ {.pages_count = 4, .pages_size = KB(16)}, {.pages_count = 1, .pages_size = KB(64)}, }; #elif FLASH_SECTOR_TOTAL == 6 static const struct flash_pages_layout stm32f4_flash_layout[] = { /* RM0368, table 5: STM32F401xC */ {.pages_count = 4, .pages_size = KB(16)}, {.pages_count = 1, .pages_size = KB(64)}, {.pages_count = 1, .pages_size = KB(128)}, }; #elif FLASH_SECTOR_TOTAL == 8 static const struct flash_pages_layout stm32f4_flash_layout[] = { /* * RM0368, table 5: STM32F401xE * RM0383, table 4: STM32F411xE * RM0390, table 4: STM32F446xx */ {.pages_count = 4, .pages_size = KB(16)}, {.pages_count = 1, .pages_size = KB(64)}, {.pages_count = 3, .pages_size = KB(128)}, }; #elif FLASH_SECTOR_TOTAL == 12 static const struct flash_pages_layout stm32f4_flash_layout[] = { /* * RM0090, table 5: STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx * RM0402, table 5: STM32F412Zx, STM32F412Vx, STM32F412Rx, STM32F412Cx */ {.pages_count = 4, .pages_size = KB(16)}, {.pages_count = 1, .pages_size = KB(64)}, {.pages_count = 7, .pages_size = KB(128)}, }; #elif FLASH_SECTOR_TOTAL == 16 static const struct flash_pages_layout stm32f4_flash_layout[] = { /* RM0430, table 5.: STM32F413xx, STM32F423xx */ {.pages_count = 4, .pages_size = KB(16)}, {.pages_count = 1, .pages_size = KB(64)}, {.pages_count = 11, .pages_size = KB(128)}, }; #elif FLASH_SECTOR_TOTAL == 24 static const struct flash_pages_layout stm32f4_flash_layout[] = { /* * RM0090, table 6: STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx * RM0386, table 4: STM32F469xx, STM32F479xx */ {.pages_count = 4, .pages_size = KB(16)}, {.pages_count = 1, .pages_size = KB(64)}, {.pages_count = 7, .pages_size = KB(128)}, {.pages_count = 4, .pages_size = KB(16)}, {.pages_count = 1, .pages_size = KB(64)}, {.pages_count = 7, .pages_size = KB(128)}, }; #else #error "Unknown flash layout" #endif /* FLASH_SECTOR_TOTAL == 5 */ #endif/* !defined(FLASH_SECTOR_TOTAL) */ void flash_stm32_page_layout(const struct device *dev, const struct flash_pages_layout **layout, size_t *layout_size) { ARG_UNUSED(dev); *layout = stm32f4_flash_layout; *layout_size = ARRAY_SIZE(stm32f4_flash_layout); } |