1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 | /*
* Copyright (c) 2017 comsuisse AG
*
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Atmel SAM MCU family Direct Memory Access (XDMAC) driver.
*/
#ifndef ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_
#define ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* XDMA_MBR_UBC */
#define XDMA_UBC_NDE (0x1u << 24)
#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)
#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24)
#define XDMA_UBC_NSEN (0x1u << 25)
#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)
#define XDMA_UBC_NSEN_UPDATED (0x1u << 25)
#define XDMA_UBC_NDEN (0x1u << 26)
#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)
#define XDMA_UBC_NDEN_UPDATED (0x1u << 26)
#define XDMA_UBC_NVIEW_SHIFT 27
#define XDMA_UBC_NVIEW_MASK (0x3u << XDMA_UBC_NVIEW_SHIFT)
#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_SHIFT)
#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_SHIFT)
#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_SHIFT)
#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_SHIFT)
/** DMA channel configuration parameters */
struct sam_xdmac_channel_config {
/** Configuration Register */
uint32_t cfg;
/** Data Stride / Memory Set Pattern Register */
uint32_t ds_msp;
/** Source Microblock Stride */
uint32_t sus;
/** Destination Microblock Stride */
uint32_t dus;
/** Channel Interrupt Enable */
uint32_t cie;
};
/** DMA transfer configuration parameters */
struct sam_xdmac_transfer_config {
/** Microblock length */
uint32_t ublen;
/** Source Address */
uint32_t sa;
/** Destination Address */
uint32_t da;
/** Block length (The length of the block is (blen+1) microblocks) */
uint32_t blen;
/** Next descriptor address */
uint32_t nda;
/** Next descriptor configuration */
uint32_t ndc;
};
/** DMA Master transfer linked list view 0 structure */
struct sam_xdmac_linked_list_desc_view0 {
/** Next Descriptor Address */
uint32_t mbr_nda;
/** Microblock Control */
uint32_t mbr_ubc;
/** Transfer Address */
uint32_t mbr_ta;
};
/** DMA Master transfer linked list view 1 structure */
struct sam_xdmac_linked_list_desc_view1 {
/** Next Descriptor Address */
uint32_t mbr_nda;
/** Microblock Control */
uint32_t mbr_ubc;
/** Source Address */
uint32_t mbr_sa;
/** Destination Address */
uint32_t mbr_da;
};
/** DMA Master transfer linked list view 2 structure */
struct sam_xdmac_linked_list_desc_view2 {
/** Next Descriptor Address */
uint32_t mbr_nda;
/** Microblock Control */
uint32_t mbr_ubc;
/** Source Address */
uint32_t mbr_sa;
/** Destination Address */
uint32_t mbr_da;
/** Configuration Register */
uint32_t mbr_cfg;
};
/** DMA Master transfer linked list view 3 structure */
struct sam_xdmac_linked_list_desc_view3 {
/** Next Descriptor Address */
uint32_t mbr_nda;
/** Microblock Control */
uint32_t mbr_ubc;
/** Source Address */
uint32_t mbr_sa;
/** Destination Address */
uint32_t mbr_da;
/** Configuration Register */
uint32_t mbr_cfg;
/** Block Control */
uint32_t mbr_bc;
/** Data Stride */
uint32_t mbr_ds;
/** Source Microblock Stride */
uint32_t mbr_sus;
/** Destination Microblock Stride */
uint32_t mbr_dus;
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_ */
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