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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 | /* Atomic operations. PowerPC32 version. Copyright (C) 2003, 2004 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003. The GNU C Library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. The GNU C Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, see <http://www.gnu.org/licenses/>. */ # define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \ ({ \ unsigned int __tmp; \ __asm__ __volatile__ ( \ "1: lwarx %0,0,%1\n" \ " subf. %0,%2,%0\n" \ " bne 2f\n" \ " stwcx. %3,0,%1\n" \ " bne- 1b\n" \ "2: " __ARCH_ACQ_INSTR \ : "=&r" (__tmp) \ : "b" (mem), "r" (oldval), "r" (newval) \ : "cr0", "memory"); \ __tmp != 0; \ }) # define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \ ({ \ unsigned int __tmp; \ __asm__ __volatile__ (__ARCH_REL_INSTR "\n" \ "1: lwarx %0,0,%1\n" \ " subf. %0,%2,%0\n" \ " bne 2f\n" \ " stwcx. %3,0,%1\n" \ " bne- 1b\n" \ "2: " \ : "=&r" (__tmp) \ : "b" (mem), "r" (oldval), "r" (newval) \ : "cr0", "memory"); \ __tmp != 0; \ }) /* Powerpc32 processors don't implement the 64-bit (doubleword) forms of load and reserve (ldarx) and store conditional (stdcx.) instructions. So for powerpc32 we stub out the 64-bit forms. */ # define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \ (abort (), 0) # define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ (abort (), (__typeof (*mem)) 0) # define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \ (abort (), 0) # define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \ (abort (), (__typeof (*mem)) 0) # define __arch_atomic_exchange_64_acq(mem, value) \ ({ abort (); (*mem) = (value); }) # define __arch_atomic_exchange_64_rel(mem, value) \ ({ abort (); (*mem) = (value); }) # define __arch_atomic_exchange_and_add_64(mem, value) \ ({ abort (); (*mem) = (value); }) # define __arch_atomic_increment_val_64(mem) \ ({ abort (); (*mem)++; }) # define __arch_atomic_decrement_val_64(mem) \ ({ abort (); (*mem)--; }) # define __arch_atomic_decrement_if_positive_64(mem) \ ({ abort (); (*mem)--; }) #ifdef _ARCH_PWR4 /* * Newer powerpc64 processors support the new "light weight" sync (lwsync) * So if the build is using -mcpu=[power4,power5,power5+,970] we can * safely use lwsync. */ # define atomic_read_barrier() __asm__ ("lwsync" ::: "memory") /* * "light weight" sync can also be used for the release barrier. */ # ifndef UP # define __ARCH_REL_INSTR "lwsync" # endif #else /* * Older powerpc32 processors don't support the new "light weight" * sync (lwsync). So the only safe option is to use normal sync * for all powerpc32 applications. */ # define atomic_read_barrier() __asm__ ("sync" ::: "memory") #endif #include <stdint.h> typedef int32_t atomic32_t; typedef uint32_t uatomic32_t; typedef int_fast32_t atomic_fast32_t; typedef uint_fast32_t uatomic_fast32_t; typedef int64_t atomic64_t; typedef uint64_t uatomic64_t; typedef int_fast64_t atomic_fast64_t; typedef uint_fast64_t uatomic_fast64_t; typedef intptr_t atomicptr_t; typedef uintptr_t uatomicptr_t; typedef intmax_t atomic_max_t; typedef uintmax_t uatomic_max_t; /* * Powerpc does not have byte and halfword forms of load and reserve and * store conditional. So for powerpc we stub out the 8- and 16-bit forms. */ #define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \ (abort (), 0) #define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \ (abort (), 0) #define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \ (abort (), 0) #define __arch_compare_and_exchange_bool_16_rel(mem, newval, oldval) \ (abort (), 0) #ifdef UP # define __ARCH_ACQ_INSTR "" # define __ARCH_REL_INSTR "" #else # define __ARCH_ACQ_INSTR "isync" # ifndef __ARCH_REL_INSTR # define __ARCH_REL_INSTR "sync" # endif #endif #ifndef MUTEX_HINT_ACQ # define MUTEX_HINT_ACQ #endif #ifndef MUTEX_HINT_REL # define MUTEX_HINT_REL #endif #define atomic_full_barrier() __asm__ ("sync" ::: "memory") #define atomic_write_barrier() __asm__ ("eieio" ::: "memory") #define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ ({ \ __typeof (*(mem)) __tmp; \ __typeof (mem) __memp = (mem); \ __asm__ __volatile__ ( \ "1: lwarx %0,0,%1\n" \ " cmpw %0,%2\n" \ " bne 2f\n" \ " stwcx. %3,0,%1\n" \ " bne- 1b\n" \ "2: " __ARCH_ACQ_INSTR \ : "=&r" (__tmp) \ : "b" (__memp), "r" (oldval), "r" (newval) \ : "cr0", "memory"); \ __tmp; \ }) #define __arch_compare_and_exchange_val_32_rel(mem, newval, oldval) \ ({ \ __typeof (*(mem)) __tmp; \ __typeof (mem) __memp = (mem); \ __asm__ __volatile__ (__ARCH_REL_INSTR "\n" \ "1: lwarx %0,0,%1\n" \ " cmpw %0,%2\n" \ " bne 2f\n" \ " stwcx. %3,0,%1\n" \ " bne- 1b\n" \ "2: " \ : "=&r" (__tmp) \ : "b" (__memp), "r" (oldval), "r" (newval) \ : "cr0", "memory"); \ __tmp; \ }) #define __arch_atomic_exchange_32_acq(mem, value) \ ({ \ __typeof (*mem) __val; \ __asm__ __volatile__ ( \ "1: lwarx %0,0,%2\n" \ " stwcx. %3,0,%2\n" \ " bne- 1b\n" \ " " __ARCH_ACQ_INSTR \ : "=&r" (__val), "=m" (*mem) \ : "b" (mem), "r" (value), "m" (*mem) \ : "cr0", "memory"); \ __val; \ }) #define __arch_atomic_exchange_32_rel(mem, value) \ ({ \ __typeof (*mem) __val; \ __asm__ __volatile__ (__ARCH_REL_INSTR "\n" \ "1: lwarx %0,0,%2\n" \ " stwcx. %3,0,%2\n" \ " bne- 1b" \ : "=&r" (__val), "=m" (*mem) \ : "b" (mem), "r" (value), "m" (*mem) \ : "cr0", "memory"); \ __val; \ }) #define __arch_atomic_exchange_and_add_32(mem, value) \ ({ \ __typeof (*mem) __val, __tmp; \ __asm__ __volatile__ ("1: lwarx %0,0,%3\n" \ " add %1,%0,%4\n" \ " stwcx. %1,0,%3\n" \ " bne- 1b" \ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ : "b" (mem), "r" (value), "m" (*mem) \ : "cr0", "memory"); \ __val; \ }) #define __arch_atomic_increment_val_32(mem) \ ({ \ __typeof (*(mem)) __val; \ __asm__ __volatile__ ("1: lwarx %0,0,%2\n" \ " addi %0,%0,1\n" \ " stwcx. %0,0,%2\n" \ " bne- 1b" \ : "=&b" (__val), "=m" (*mem) \ : "b" (mem), "m" (*mem) \ : "cr0", "memory"); \ __val; \ }) #define __arch_atomic_decrement_val_32(mem) \ ({ \ __typeof (*(mem)) __val; \ __asm__ __volatile__ ("1: lwarx %0,0,%2\n" \ " subi %0,%0,1\n" \ " stwcx. %0,0,%2\n" \ " bne- 1b" \ : "=&b" (__val), "=m" (*mem) \ : "b" (mem), "m" (*mem) \ : "cr0", "memory"); \ __val; \ }) #define __arch_atomic_decrement_if_positive_32(mem) \ ({ int __val, __tmp; \ __asm__ __volatile__ ("1: lwarx %0,0,%3\n" \ " cmpwi 0,%0,0\n" \ " addi %1,%0,-1\n" \ " ble 2f\n" \ " stwcx. %1,0,%3\n" \ " bne- 1b\n" \ "2: " __ARCH_ACQ_INSTR \ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ : "b" (mem), "m" (*mem) \ : "cr0", "memory"); \ __val; \ }) #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ ({ \ __typeof (*(mem)) __result; \ if (sizeof (*mem) == 4) \ __result = __arch_compare_and_exchange_val_32_acq(mem, newval, oldval); \ else if (sizeof (*mem) == 8) \ __result = __arch_compare_and_exchange_val_64_acq(mem, newval, oldval); \ else \ abort (); \ __result; \ }) #define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \ ({ \ __typeof (*(mem)) __result; \ if (sizeof (*mem) == 4) \ __result = __arch_compare_and_exchange_val_32_rel(mem, newval, oldval); \ else if (sizeof (*mem) == 8) \ __result = __arch_compare_and_exchange_val_64_rel(mem, newval, oldval); \ else \ abort (); \ __result; \ }) #define atomic_exchange_acq(mem, value) \ ({ \ __typeof (*(mem)) __result; \ if (sizeof (*mem) == 4) \ __result = __arch_atomic_exchange_32_acq (mem, value); \ else if (sizeof (*mem) == 8) \ __result = __arch_atomic_exchange_64_acq (mem, value); \ else \ abort (); \ __result; \ }) #define atomic_exchange_rel(mem, value) \ ({ \ __typeof (*(mem)) __result; \ if (sizeof (*mem) == 4) \ __result = __arch_atomic_exchange_32_rel (mem, value); \ else if (sizeof (*mem) == 8) \ __result = __arch_atomic_exchange_64_rel (mem, value); \ else \ abort (); \ __result; \ }) #define atomic_exchange_and_add(mem, value) \ ({ \ __typeof (*(mem)) __result; \ if (sizeof (*mem) == 4) \ __result = __arch_atomic_exchange_and_add_32 (mem, value); \ else if (sizeof (*mem) == 8) \ __result = __arch_atomic_exchange_and_add_64 (mem, value); \ else \ abort (); \ __result; \ }) #define atomic_increment_val(mem) \ ({ \ __typeof (*(mem)) __result; \ if (sizeof (*(mem)) == 4) \ __result = __arch_atomic_increment_val_32 (mem); \ else if (sizeof (*(mem)) == 8) \ __result = __arch_atomic_increment_val_64 (mem); \ else \ abort (); \ __result; \ }) #define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; }) #define atomic_decrement_val(mem) \ ({ \ __typeof (*(mem)) __result; \ if (sizeof (*(mem)) == 4) \ __result = __arch_atomic_decrement_val_32 (mem); \ else if (sizeof (*(mem)) == 8) \ __result = __arch_atomic_decrement_val_64 (mem); \ else \ abort (); \ __result; \ }) #define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; }) /* Decrement *MEM if it is > 0, and return the old value. */ #define atomic_decrement_if_positive(mem) \ ({ __typeof (*(mem)) __result; \ if (sizeof (*mem) == 4) \ __result = __arch_atomic_decrement_if_positive_32 (mem); \ else if (sizeof (*mem) == 8) \ __result = __arch_atomic_decrement_if_positive_64 (mem); \ else \ abort (); \ __result; \ }) |