Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 | #ifndef __eth_defs_h
#define __eth_defs_h
/*
* This file is autogenerated from
* file: eth.r
* id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
* last modfied: Mon Jan 9 06:06:41 2006
*
* by /n/asic/design/tools/rdesc/rdes2c eth.r
* id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope eth */
/* Register rw_ma0_lo, scope eth, type rw */
typedef struct {
unsigned int addr : 32;
} reg_eth_rw_ma0_lo;
#define REG_RD_ADDR_eth_rw_ma0_lo 0
#define REG_WR_ADDR_eth_rw_ma0_lo 0
/* Register rw_ma0_hi, scope eth, type rw */
typedef struct {
unsigned int addr : 16;
unsigned int dummy1 : 16;
} reg_eth_rw_ma0_hi;
#define REG_RD_ADDR_eth_rw_ma0_hi 4
#define REG_WR_ADDR_eth_rw_ma0_hi 4
/* Register rw_ma1_lo, scope eth, type rw */
typedef struct {
unsigned int addr : 32;
} reg_eth_rw_ma1_lo;
#define REG_RD_ADDR_eth_rw_ma1_lo 8
#define REG_WR_ADDR_eth_rw_ma1_lo 8
/* Register rw_ma1_hi, scope eth, type rw */
typedef struct {
unsigned int addr : 16;
unsigned int dummy1 : 16;
} reg_eth_rw_ma1_hi;
#define REG_RD_ADDR_eth_rw_ma1_hi 12
#define REG_WR_ADDR_eth_rw_ma1_hi 12
/* Register rw_ga_lo, scope eth, type rw */
typedef struct {
unsigned int tbl : 32;
} reg_eth_rw_ga_lo;
#define REG_RD_ADDR_eth_rw_ga_lo 16
#define REG_WR_ADDR_eth_rw_ga_lo 16
/* Register rw_ga_hi, scope eth, type rw */
typedef struct {
unsigned int tbl : 32;
} reg_eth_rw_ga_hi;
#define REG_RD_ADDR_eth_rw_ga_hi 20
#define REG_WR_ADDR_eth_rw_ga_hi 20
/* Register rw_gen_ctrl, scope eth, type rw */
typedef struct {
unsigned int en : 1;
unsigned int phy : 2;
unsigned int protocol : 1;
unsigned int loopback : 1;
unsigned int flow_ctrl : 1;
unsigned int gtxclk_out : 1;
unsigned int phyrst_n : 1;
unsigned int dummy1 : 24;
} reg_eth_rw_gen_ctrl;
#define REG_RD_ADDR_eth_rw_gen_ctrl 24
#define REG_WR_ADDR_eth_rw_gen_ctrl 24
/* Register rw_rec_ctrl, scope eth, type rw */
typedef struct {
unsigned int ma0 : 1;
unsigned int ma1 : 1;
unsigned int individual : 1;
unsigned int broadcast : 1;
unsigned int undersize : 1;
unsigned int oversize : 1;
unsigned int bad_crc : 1;
unsigned int duplex : 1;
unsigned int max_size : 16;
unsigned int dummy1 : 8;
} reg_eth_rw_rec_ctrl;
#define REG_RD_ADDR_eth_rw_rec_ctrl 28
#define REG_WR_ADDR_eth_rw_rec_ctrl 28
/* Register rw_tr_ctrl, scope eth, type rw */
typedef struct {
unsigned int crc : 1;
unsigned int pad : 1;
unsigned int retry : 1;
unsigned int ignore_col : 1;
unsigned int cancel : 1;
unsigned int hsh_delay : 1;
unsigned int ignore_crs : 1;
unsigned int carrier_ext : 1;
unsigned int dummy1 : 24;
} reg_eth_rw_tr_ctrl;
#define REG_RD_ADDR_eth_rw_tr_ctrl 32
#define REG_WR_ADDR_eth_rw_tr_ctrl 32
/* Register rw_clr_err, scope eth, type rw */
typedef struct {
unsigned int clr : 1;
unsigned int dummy1 : 31;
} reg_eth_rw_clr_err;
#define REG_RD_ADDR_eth_rw_clr_err 36
#define REG_WR_ADDR_eth_rw_clr_err 36
/* Register rw_mgm_ctrl, scope eth, type rw */
typedef struct {
unsigned int mdio : 1;
unsigned int mdoe : 1;
unsigned int mdc : 1;
unsigned int dummy1 : 29;
} reg_eth_rw_mgm_ctrl;
#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
/* Register r_stat, scope eth, type r */
typedef struct {
unsigned int mdio : 1;
unsigned int exc_col : 1;
unsigned int urun : 1;
unsigned int clk_125 : 1;
unsigned int dummy1 : 28;
} reg_eth_r_stat;
#define REG_RD_ADDR_eth_r_stat 44
/* Register rs_rec_cnt, scope eth, type rs */
typedef struct {
unsigned int crc_err : 8;
unsigned int align_err : 8;
unsigned int oversize : 8;
unsigned int congestion : 8;
} reg_eth_rs_rec_cnt;
#define REG_RD_ADDR_eth_rs_rec_cnt 48
/* Register r_rec_cnt, scope eth, type r */
typedef struct {
unsigned int crc_err : 8;
unsigned int align_err : 8;
unsigned int oversize : 8;
unsigned int congestion : 8;
} reg_eth_r_rec_cnt;
#define REG_RD_ADDR_eth_r_rec_cnt 52
/* Register rs_tr_cnt, scope eth, type rs */
typedef struct {
unsigned int single_col : 8;
unsigned int mult_col : 8;
unsigned int late_col : 8;
unsigned int deferred : 8;
} reg_eth_rs_tr_cnt;
#define REG_RD_ADDR_eth_rs_tr_cnt 56
/* Register r_tr_cnt, scope eth, type r */
typedef struct {
unsigned int single_col : 8;
unsigned int mult_col : 8;
unsigned int late_col : 8;
unsigned int deferred : 8;
} reg_eth_r_tr_cnt;
#define REG_RD_ADDR_eth_r_tr_cnt 60
/* Register rs_phy_cnt, scope eth, type rs */
typedef struct {
unsigned int carrier_loss : 8;
unsigned int sqe_err : 8;
unsigned int dummy1 : 16;
} reg_eth_rs_phy_cnt;
#define REG_RD_ADDR_eth_rs_phy_cnt 64
/* Register r_phy_cnt, scope eth, type r */
typedef struct {
unsigned int carrier_loss : 8;
unsigned int sqe_err : 8;
unsigned int dummy1 : 16;
} reg_eth_r_phy_cnt;
#define REG_RD_ADDR_eth_r_phy_cnt 68
/* Register rw_test_ctrl, scope eth, type rw */
typedef struct {
unsigned int snmp_inc : 1;
unsigned int snmp : 1;
unsigned int backoff : 1;
unsigned int dummy1 : 29;
} reg_eth_rw_test_ctrl;
#define REG_RD_ADDR_eth_rw_test_ctrl 72
#define REG_WR_ADDR_eth_rw_test_ctrl 72
/* Register rw_intr_mask, scope eth, type rw */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_rw_intr_mask;
#define REG_RD_ADDR_eth_rw_intr_mask 76
#define REG_WR_ADDR_eth_rw_intr_mask 76
/* Register rw_ack_intr, scope eth, type rw */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_rw_ack_intr;
#define REG_RD_ADDR_eth_rw_ack_intr 80
#define REG_WR_ADDR_eth_rw_ack_intr 80
/* Register r_intr, scope eth, type r */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_r_intr;
#define REG_RD_ADDR_eth_r_intr 84
/* Register r_masked_intr, scope eth, type r */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_r_masked_intr;
#define REG_RD_ADDR_eth_r_masked_intr 88
/* Constants */
enum {
regk_eth_discard = 0x00000000,
regk_eth_ether = 0x00000000,
regk_eth_full = 0x00000001,
regk_eth_gmii = 0x00000003,
regk_eth_gtxclk = 0x00000001,
regk_eth_half = 0x00000000,
regk_eth_hsh = 0x00000001,
regk_eth_mii = 0x00000001,
regk_eth_mii_arec = 0x00000002,
regk_eth_mii_clk = 0x00000000,
regk_eth_no = 0x00000000,
regk_eth_phyrst = 0x00000000,
regk_eth_rec = 0x00000001,
regk_eth_rw_ga_hi_default = 0x00000000,
regk_eth_rw_ga_lo_default = 0x00000000,
regk_eth_rw_gen_ctrl_default = 0x00000000,
regk_eth_rw_intr_mask_default = 0x00000000,
regk_eth_rw_ma0_hi_default = 0x00000000,
regk_eth_rw_ma0_lo_default = 0x00000000,
regk_eth_rw_ma1_hi_default = 0x00000000,
regk_eth_rw_ma1_lo_default = 0x00000000,
regk_eth_rw_mgm_ctrl_default = 0x00000000,
regk_eth_rw_test_ctrl_default = 0x00000000,
regk_eth_size1518 = 0x000005ee,
regk_eth_size1522 = 0x000005f2,
regk_eth_yes = 0x00000001
};
#endif /* __eth_defs_h */
|