Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 | /*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_address_map.h - Contains the register mapping for the ET1310
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef _ET1310_ADDRESS_MAP_H_
#define _ET1310_ADDRESS_MAP_H_
/* START OF GLOBAL REGISTER ADDRESS MAP */
typedef union _Q_ADDR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:22; // bits 10-31
u32 addr:10; // bits 0-9
#else
u32 addr:10; // bits 0-9
u32 unused:22; // bits 10-31
#endif
} bits;
} Q_ADDR_t, *PQ_ADDR_t;
/*
* structure for tx queue start address reg in global address map
* located at address 0x0000
* Defined earlier (Q_ADDR_t)
*/
/*
* structure for tx queue end address reg in global address map
* located at address 0x0004
* Defined earlier (Q_ADDR_t)
*/
/*
* structure for rx queue start address reg in global address map
* located at address 0x0008
* Defined earlier (Q_ADDR_t)
*/
/*
* structure for rx queue end address reg in global address map
* located at address 0x000C
* Defined earlier (Q_ADDR_t)
*/
/*
* structure for power management control status reg in global address map
* located at address 0x0010
*/
typedef union _PM_CSR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:22; // bits 10-31
u32 pm_jagcore_rx_rdy:1; // bit 9
u32 pm_jagcore_tx_rdy:1; // bit 8
u32 pm_phy_lped_en:1; // bit 7
u32 pm_phy_sw_coma:1; // bit 6
u32 pm_rxclk_gate:1; // bit 5
u32 pm_txclk_gate:1; // bit 4
u32 pm_sysclk_gate:1; // bit 3
u32 pm_jagcore_rx_en:1; // bit 2
u32 pm_jagcore_tx_en:1; // bit 1
u32 pm_gigephy_en:1; // bit 0
#else
u32 pm_gigephy_en:1; // bit 0
u32 pm_jagcore_tx_en:1; // bit 1
u32 pm_jagcore_rx_en:1; // bit 2
u32 pm_sysclk_gate:1; // bit 3
u32 pm_txclk_gate:1; // bit 4
u32 pm_rxclk_gate:1; // bit 5
u32 pm_phy_sw_coma:1; // bit 6
u32 pm_phy_lped_en:1; // bit 7
u32 pm_jagcore_tx_rdy:1; // bit 8
u32 pm_jagcore_rx_rdy:1; // bit 9
u32 unused:22; // bits 10-31
#endif
} bits;
} PM_CSR_t, *PPM_CSR_t;
/*
* structure for interrupt status reg in global address map
* located at address 0x0018
*/
typedef union _INTERRUPT_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused5:11; // bits 21-31
u32 slv_timeout:1; // bit 20
u32 mac_stat_interrupt:1; // bit 19
u32 rxmac_interrupt:1; // bit 18
u32 txmac_interrupt:1; // bit 17
u32 phy_interrupt:1; // bit 16
u32 wake_on_lan:1; // bit 15
u32 watchdog_interrupt:1; // bit 14
u32 unused4:4; // bits 10-13
u32 rxdma_err:1; // bit 9
u32 rxdma_pkt_stat_ring_low:1; // bit 8
u32 rxdma_fb_ring1_low:1; // bit 7
u32 rxdma_fb_ring0_low:1; // bit 6
u32 rxdma_xfr_done:1; // bit 5
u32 txdma_err:1; // bit 4
u32 txdma_isr:1; // bit 3
u32 unused3:1; // bit 2
u32 unused2:1; // bit 1
u32 unused1:1; // bit 0
#else
u32 unused1:1; // bit 0
u32 unused2:1; // bit 1
u32 unused3:1; // bit 2
u32 txdma_isr:1; // bit 3
u32 txdma_err:1; // bit 4
u32 rxdma_xfr_done:1; // bit 5
u32 rxdma_fb_ring0_low:1; // bit 6
u32 rxdma_fb_ring1_low:1; // bit 7
u32 rxdma_pkt_stat_ring_low:1; // bit 8
u32 rxdma_err:1; // bit 9
u32 unused4:4; // bits 10-13
u32 watchdog_interrupt:1; // bit 14
u32 wake_on_lan:1; // bit 15
u32 phy_interrupt:1; // bit 16
u32 txmac_interrupt:1; // bit 17
u32 rxmac_interrupt:1; // bit 18
u32 mac_stat_interrupt:1; // bit 19
u32 slv_timeout:1; // bit 20
u32 unused5:11; // bits 21-31
#endif
} bits;
} INTERRUPT_t, *PINTERRUPT_t;
/*
* structure for interrupt mask reg in global address map
* located at address 0x001C
* Defined earlier (INTERRUPT_t), but 'watchdog_interrupt' is not used.
*/
/*
* structure for interrupt alias clear mask reg in global address map
* located at address 0x0020
* Defined earlier (INTERRUPT_t)
*/
/*
* structure for interrupt status alias reg in global address map
* located at address 0x0024
* Defined earlier (INTERRUPT_t)
*/
/*
* structure for software reset reg in global address map
* located at address 0x0028
*/
typedef union _SW_RESET_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 selfclr_disable:1; // bit 31
u32 unused:24; // bits 7-30
u32 mmc_sw_reset:1; // bit 6
u32 mac_stat_sw_reset:1; // bit 5
u32 mac_sw_reset:1; // bit 4
u32 rxmac_sw_reset:1; // bit 3
u32 txmac_sw_reset:1; // bit 2
u32 rxdma_sw_reset:1; // bit 1
u32 txdma_sw_reset:1; // bit 0
#else
u32 txdma_sw_reset:1; // bit 0
u32 rxdma_sw_reset:1; // bit 1
u32 txmac_sw_reset:1; // bit 2
u32 rxmac_sw_reset:1; // bit 3
u32 mac_sw_reset:1; // bit 4
u32 mac_stat_sw_reset:1; // bit 5
u32 mmc_sw_reset:1; // bit 6
u32 unused:24; // bits 7-30
u32 selfclr_disable:1; // bit 31
#endif
} bits;
} SW_RESET_t, *PSW_RESET_t;
/*
* structure for SLV Timer reg in global address map
* located at address 0x002C
*/
typedef union _SLV_TIMER_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:8; // bits 24-31
u32 timer_ini:24; // bits 0-23
#else
u32 timer_ini:24; // bits 0-23
u32 unused:8; // bits 24-31
#endif
} bits;
} SLV_TIMER_t, *PSLV_TIMER_t;
/*
* structure for MSI Configuration reg in global address map
* located at address 0x0030
*/
typedef union _MSI_CONFIG_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused1:13; // bits 19-31
u32 msi_tc:3; // bits 16-18
u32 unused2:11; // bits 5-15
u32 msi_vector:5; // bits 0-4
#else
u32 msi_vector:5; // bits 0-4
u32 unused2:11; // bits 5-15
u32 msi_tc:3; // bits 16-18
u32 unused1:13; // bits 19-31
#endif
} bits;
} MSI_CONFIG_t, *PMSI_CONFIG_t;
/*
* structure for Loopback reg in global address map
* located at address 0x0034
*/
typedef union _LOOPBACK_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:30; // bits 2-31
u32 dma_loopback:1; // bit 1
u32 mac_loopback:1; // bit 0
#else
u32 mac_loopback:1; // bit 0
u32 dma_loopback:1; // bit 1
u32 unused:30; // bits 2-31
#endif
} bits;
} LOOPBACK_t, *PLOOPBACK_t;
/*
* GLOBAL Module of JAGCore Address Mapping
* Located at address 0x0000
*/
typedef struct _GLOBAL_t { // Location:
Q_ADDR_t txq_start_addr; // 0x0000
Q_ADDR_t txq_end_addr; // 0x0004
Q_ADDR_t rxq_start_addr; // 0x0008
Q_ADDR_t rxq_end_addr; // 0x000C
PM_CSR_t pm_csr; // 0x0010
u32 unused; // 0x0014
INTERRUPT_t int_status; // 0x0018
INTERRUPT_t int_mask; // 0x001C
INTERRUPT_t int_alias_clr_en; // 0x0020
INTERRUPT_t int_status_alias; // 0x0024
SW_RESET_t sw_reset; // 0x0028
SLV_TIMER_t slv_timer; // 0x002C
MSI_CONFIG_t msi_config; // 0x0030
LOOPBACK_t loopback; // 0x0034
u32 watchdog_timer; // 0x0038
} GLOBAL_t, *PGLOBAL_t;
/* END OF GLOBAL REGISTER ADDRESS MAP */
/* START OF TXDMA REGISTER ADDRESS MAP */
/*
* structure for txdma control status reg in txdma address map
* located at address 0x1000
*/
typedef union _TXDMA_CSR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused2:19; // bits 13-31
u32 traffic_class:4; // bits 9-12
u32 sngl_epkt_mode:1; // bit 8
u32 cache_thrshld:4; // bits 4-7
u32 unused1:2; // bits 2-3
u32 drop_TLP_disable:1; // bit 1
u32 halt:1; // bit 0
#else
u32 halt:1; // bit 0
u32 drop_TLP_disable:1; // bit 1
u32 unused1:2; // bits 2-3
u32 cache_thrshld:4; // bits 4-7
u32 sngl_epkt_mode:1; // bit 8
u32 traffic_class:4; // bits 9-12
u32 unused2:19; // bits 13-31
#endif
} bits;
} TXDMA_CSR_t, *PTXDMA_CSR_t;
/*
* structure for txdma packet ring base address hi reg in txdma address map
* located at address 0x1004
* Defined earlier (u32)
*/
/*
* structure for txdma packet ring base address low reg in txdma address map
* located at address 0x1008
* Defined earlier (u32)
*/
/*
* structure for txdma packet ring number of descriptor reg in txdma address
* map. Located at address 0x100C
*/
typedef union _TXDMA_PR_NUM_DES_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:22; // bits 10-31
u32 pr_ndes:10; // bits 0-9
#else
u32 pr_ndes:10; // bits 0-9
u32 unused:22; // bits 10-31
#endif
} bits;
} TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
typedef union _DMA10W_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:21; // bits 11-31
u32 wrap:1; // bit 10
u32 val:10; // bits 0-9
#else
u32 val:10; // bits 0-9
u32 wrap:1; // bit 10
u32 unused:21; // bits 11-31
#endif
} bits;
} DMA10W_t, *PDMA10W_t;
/*
* structure for txdma tx queue write address reg in txdma address map
* located at address 0x1010
* Defined earlier (DMA10W_t)
*/
/*
* structure for txdma tx queue write address external reg in txdma address map
* located at address 0x1014
* Defined earlier (DMA10W_t)
*/
/*
* structure for txdma tx queue read address reg in txdma address map
* located at address 0x1018
* Defined earlier (DMA10W_t)
*/
/*
* structure for txdma status writeback address hi reg in txdma address map
* located at address 0x101C
* Defined earlier (u32)
*/
/*
* structure for txdma status writeback address lo reg in txdma address map
* located at address 0x1020
* Defined earlier (u32)
*/
/*
* structure for txdma service request reg in txdma address map
* located at address 0x1024
* Defined earlier (DMA10W_t)
*/
/*
* structure for txdma service complete reg in txdma address map
* located at address 0x1028
* Defined earlier (DMA10W_t)
*/
typedef union _DMA4W_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:27; // bits 5-31
u32 wrap:1; // bit 4
u32 val:4; // bit 0-3
#else
u32 val:4; // bits 0-3
u32 wrap:1; // bit 4
u32 unused:27; // bits 5-31
#endif
} bits;
} DMA4W_t, *PDMA4W_t;
/*
* structure for txdma tx descriptor cache read index reg in txdma address map
* located at address 0x102C
* Defined earlier (DMA4W_t)
*/
/*
* structure for txdma tx descriptor cache write index reg in txdma address map
* located at address 0x1030
* Defined earlier (DMA4W_t)
*/
/*
* structure for txdma error reg in txdma address map
* located at address 0x1034
*/
typedef union _TXDMA_ERROR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused3:22; // bits 10-31
u32 WrbkRewind:1; // bit 9
u32 WrbkResend:1; // bit 8
u32 unused2:2; // bits 6-7
u32 DescrRewind:1; // bit 5
u32 DescrResend:1; // bit 4
u32 unused1:2; // bits 2-3
u32 PyldRewind:1; // bit 1
u32 PyldResend:1; // bit 0
#else
u32 PyldResend:1; // bit 0
u32 PyldRewind:1; // bit 1
u32 unused1:2; // bits 2-3
u32 DescrResend:1; // bit 4
u32 DescrRewind:1; // bit 5
u32 unused2:2; // bits 6-7
u32 WrbkResend:1; // bit 8
u32 WrbkRewind:1; // bit 9
u32 unused3:22; // bits 10-31
#endif
} bits;
} TXDMA_ERROR_t, *PTXDMA_ERROR_t;
/*
* Tx DMA Module of JAGCore Address Mapping
* Located at address 0x1000
*/
typedef struct _TXDMA_t { // Location:
TXDMA_CSR_t csr; // 0x1000
u32 pr_base_hi; // 0x1004
u32 pr_base_lo; // 0x1008
TXDMA_PR_NUM_DES_t pr_num_des; // 0x100C
DMA10W_t txq_wr_addr; // 0x1010
DMA10W_t txq_wr_addr_ext; // 0x1014
DMA10W_t txq_rd_addr; // 0x1018
u32 dma_wb_base_hi; // 0x101C
u32 dma_wb_base_lo; // 0x1020
DMA10W_t service_request; // 0x1024
DMA10W_t service_complete; // 0x1028
DMA4W_t cache_rd_index; // 0x102C
DMA4W_t cache_wr_index; // 0x1030
TXDMA_ERROR_t TxDmaError; // 0x1034
u32 DescAbortCount; // 0x1038
u32 PayloadAbortCnt; // 0x103c
u32 WriteBackAbortCnt; // 0x1040
u32 DescTimeoutCnt; // 0x1044
u32 PayloadTimeoutCnt; // 0x1048
u32 WriteBackTimeoutCnt; // 0x104c
u32 DescErrorCount; // 0x1050
u32 PayloadErrorCnt; // 0x1054
u32 WriteBackErrorCnt; // 0x1058
u32 DroppedTLPCount; // 0x105c
DMA10W_t NewServiceComplete; // 0x1060
u32 EthernetPacketCount; // 0x1064
} TXDMA_t, *PTXDMA_t;
/* END OF TXDMA REGISTER ADDRESS MAP */
/* START OF RXDMA REGISTER ADDRESS MAP */
/*
* structure for control status reg in rxdma address map
* Located at address 0x2000
*/
typedef union _RXDMA_CSR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused2:14; // bits 18-31
u32 halt_status:1; // bit 17
u32 pkt_done_flush:1; // bit 16
u32 pkt_drop_disable:1; // bit 15
u32 unused1:1; // bit 14
u32 fbr1_enable:1; // bit 13
u32 fbr1_size:2; // bits 11-12
u32 fbr0_enable:1; // bit 10
u32 fbr0_size:2; // bits 8-9
u32 dma_big_endian:1; // bit 7
u32 pkt_big_endian:1; // bit 6
u32 psr_big_endian:1; // bit 5
u32 fbr_big_endian:1; // bit 4
u32 tc:3; // bits 1-3
u32 halt:1; // bit 0
#else
u32 halt:1; // bit 0
u32 tc:3; // bits 1-3
u32 fbr_big_endian:1; // bit 4
u32 psr_big_endian:1; // bit 5
u32 pkt_big_endian:1; // bit 6
u32 dma_big_endian:1; // bit 7
u32 fbr0_size:2; // bits 8-9
u32 fbr0_enable:1; // bit 10
u32 fbr1_size:2; // bits 11-12
u32 fbr1_enable:1; // bit 13
u32 unused1:1; // bit 14
u32 pkt_drop_disable:1; // bit 15
u32 pkt_done_flush:1; // bit 16
u32 halt_status:1; // bit 17
u32 unused2:14; // bits 18-31
#endif
} bits;
} RXDMA_CSR_t, *PRXDMA_CSR_t;
/*
* structure for dma writeback lo reg in rxdma address map
* located at address 0x2004
* Defined earlier (u32)
*/
/*
* structure for dma writeback hi reg in rxdma address map
* located at address 0x2008
* Defined earlier (u32)
*/
/*
* structure for number of packets done reg in rxdma address map
* located at address 0x200C
*/
typedef union _RXDMA_NUM_PKT_DONE_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:24; // bits 8-31
u32 num_done:8; // bits 0-7
#else
u32 num_done:8; // bits 0-7
u32 unused:24; // bits 8-31
#endif
} bits;
} RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
/*
* structure for max packet time reg in rxdma address map
* located at address 0x2010
*/
typedef union _RXDMA_MAX_PKT_TIME_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:14; // bits 18-31
u32 time_done:18; // bits 0-17
#else
u32 time_done:18; // bits 0-17
u32 unused:14; // bits 18-31
#endif
} bits;
} RXDMA_MAX_PKT_TIME_t, *PRXDMA_MAX_PKT_TIME_t;
/*
* structure for rx queue read address reg in rxdma address map
* located at address 0x2014
* Defined earlier (DMA10W_t)
*/
/*
* structure for rx queue read address external reg in rxdma address map
* located at address 0x2018
* Defined earlier (DMA10W_t)
*/
/*
* structure for rx queue write address reg in rxdma address map
* located at address 0x201C
* Defined earlier (DMA10W_t)
*/
/*
* structure for packet status ring base address lo reg in rxdma address map
* located at address 0x2020
* Defined earlier (u32)
*/
/*
* structure for packet status ring base address hi reg in rxdma address map
* located at address 0x2024
* Defined earlier (u32)
*/
/*
* structure for packet status ring number of descriptors reg in rxdma address
* map. Located at address 0x2028
*/
typedef union _RXDMA_PSR_NUM_DES_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:20; // bits 12-31
u32 psr_ndes:12; // bit 0-11
#else
u32 psr_ndes:12; // bit 0-11
u32 unused:20; // bits 12-31
#endif
} bits;
} RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
/*
* structure for packet status ring available offset reg in rxdma address map
* located at address 0x202C
*/
typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:19; // bits 13-31
u32 psr_avail_wrap:1; // bit 12
u32 psr_avail:12; // bit 0-11
#else
u32 psr_avail:12; // bit 0-11
u32 psr_avail_wrap:1; // bit 12
u32 unused:19; // bits 13-31
#endif
} bits;
} RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
/*
* structure for packet status ring full offset reg in rxdma address map
* located at address 0x2030
*/
typedef union _RXDMA_PSR_FULL_OFFSET_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:19; // bits 13-31
u32 psr_full_wrap:1; // bit 12
u32 psr_full:12; // bit 0-11
#else
u32 psr_full:12; // bit 0-11
u32 psr_full_wrap:1; // bit 12
u32 unused:19; // bits 13-31
#endif
} bits;
} RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
/*
* structure for packet status ring access index reg in rxdma address map
* located at address 0x2034
*/
typedef union _RXDMA_PSR_ACCESS_INDEX_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:27; // bits 5-31
u32 psr_ai:5; // bits 0-4
#else
u32 psr_ai:5; // bits 0-4
u32 unused:27; // bits 5-31
#endif
} bits;
} RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
/*
* structure for packet status ring minimum descriptors reg in rxdma address
* map. Located at address 0x2038
*/
typedef union _RXDMA_PSR_MIN_DES_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:20; // bits 12-31
u32 psr_min:12; // bits 0-11
#else
u32 psr_min:12; // bits 0-11
u32 unused:20; // bits 12-31
#endif
} bits;
} RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
/*
* structure for free buffer ring base lo address reg in rxdma address map
* located at address 0x203C
* Defined earlier (u32)
*/
/*
* structure for free buffer ring base hi address reg in rxdma address map
* located at address 0x2040
* Defined earlier (u32)
*/
/*
* structure for free buffer ring number of descriptors reg in rxdma address
* map. Located at address 0x2044
*/
typedef union _RXDMA_FBR_NUM_DES_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:22; // bits 10-31
u32 fbr_ndesc:10; // bits 0-9
#else
u32 fbr_ndesc:10; // bits 0-9
u32 unused:22; // bits 10-31
#endif
} bits;
} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
/*
* structure for free buffer ring 0 available offset reg in rxdma address map
* located at address 0x2048
* Defined earlier (DMA10W_t)
*/
/*
* structure for free buffer ring 0 full offset reg in rxdma address map
* located at address 0x204C
* Defined earlier (DMA10W_t)
*/
/*
* structure for free buffer cache 0 full offset reg in rxdma address map
* located at address 0x2050
*/
typedef union _RXDMA_FBC_RD_INDEX_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:27; // bits 5-31
u32 fbc_rdi:5; // bit 0-4
#else
u32 fbc_rdi:5; // bit 0-4
u32 unused:27; // bits 5-31
#endif
} bits;
} RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
/*
* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
* located at address 0x2054
*/
typedef union _RXDMA_FBR_MIN_DES_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:22; // bits 10-31
u32 fbr_min:10; // bits 0-9
#else
u32 fbr_min:10; // bits 0-9
u32 unused:22; // bits 10-31
#endif
} bits;
} RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
/*
* structure for free buffer ring 1 base address lo reg in rxdma address map
* located at address 0x2058 - 0x205C
* Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
*/
/*
* structure for free buffer ring 1 number of descriptors reg in rxdma address
* map. Located at address 0x2060
* Defined earlier (RXDMA_FBR_NUM_DES_t)
*/
/*
* structure for free buffer ring 1 available offset reg in rxdma address map
* located at address 0x2064
* Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
*/
/*
* structure for free buffer ring 1 full offset reg in rxdma address map
* located at address 0x2068
* Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
*/
/*
* structure for free buffer cache 1 read index reg in rxdma address map
* located at address 0x206C
* Defined Earlier (RXDMA_FBC_RD_INDEX_t)
*/
/*
* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
* located at address 0x2070
* Defined Earlier (RXDMA_FBR_MIN_DES_t)
*/
/*
* Rx DMA Module of JAGCore Address Mapping
* Located at address 0x2000
*/
typedef struct _RXDMA_t { // Location:
RXDMA_CSR_t csr; // 0x2000
u32 dma_wb_base_lo; // 0x2004
u32 dma_wb_base_hi; // 0x2008
RXDMA_NUM_PKT_DONE_t num_pkt_done; // 0x200C
RXDMA_MAX_PKT_TIME_t max_pkt_time; // 0x2010
DMA10W_t rxq_rd_addr; // 0x2014
DMA10W_t rxq_rd_addr_ext; // 0x2018
DMA10W_t rxq_wr_addr; // 0x201C
u32 psr_base_lo; // 0x2020
u32 psr_base_hi; // 0x2024
RXDMA_PSR_NUM_DES_t psr_num_des; // 0x2028
RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset; // 0x202C
RXDMA_PSR_FULL_OFFSET_t psr_full_offset; // 0x2030
RXDMA_PSR_ACCESS_INDEX_t psr_access_index; // 0x2034
RXDMA_PSR_MIN_DES_t psr_min_des; // 0x2038
u32 fbr0_base_lo; // 0x203C
u32 fbr0_base_hi; // 0x2040
RXDMA_FBR_NUM_DES_t fbr0_num_des; // 0x2044
DMA10W_t fbr0_avail_offset; // 0x2048
DMA10W_t fbr0_full_offset; // 0x204C
RXDMA_FBC_RD_INDEX_t fbr0_rd_index; // 0x2050
RXDMA_FBR_MIN_DES_t fbr0_min_des; // 0x2054
u32 fbr1_base_lo; // 0x2058
u32 fbr1_base_hi; // 0x205C
RXDMA_FBR_NUM_DES_t fbr1_num_des; // 0x2060
DMA10W_t fbr1_avail_offset; // 0x2064
DMA10W_t fbr1_full_offset; // 0x2068
RXDMA_FBC_RD_INDEX_t fbr1_rd_index; // 0x206C
RXDMA_FBR_MIN_DES_t fbr1_min_des; // 0x2070
} RXDMA_t, *PRXDMA_t;
/* END OF RXDMA REGISTER ADDRESS MAP */
/* START OF TXMAC REGISTER ADDRESS MAP */
/*
* structure for control reg in txmac address map
* located at address 0x3000
*/
typedef union _TXMAC_CTL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:24; // bits 8-31
u32 cklseg_diable:1; // bit 7
u32 ckbcnt_disable:1; // bit 6
u32 cksegnum:1; // bit 5
u32 async_disable:1; // bit 4
u32 fc_disable:1; // bit 3
u32 mcif_disable:1; // bit 2
u32 mif_disable:1; // bit 1
u32 txmac_en:1; // bit 0
#else
u32 txmac_en:1; // bit 0
u32 mif_disable:1; // bit 1 mac interface
u32 mcif_disable:1; // bit 2 mem. contr. interface
u32 fc_disable:1; // bit 3
u32 async_disable:1; // bit 4
u32 cksegnum:1; // bit 5
u32 ckbcnt_disable:1; // bit 6
u32 cklseg_diable:1; // bit 7
u32 unused:24; // bits 8-31
#endif
} bits;
} TXMAC_CTL_t, *PTXMAC_CTL_t;
/*
* structure for shadow pointer reg in txmac address map
* located at address 0x3004
*/
typedef union _TXMAC_SHADOW_PTR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved2:5; // bits 27-31
u32 txq_rd_ptr:11; // bits 16-26
u32 reserved:5; // bits 11-15
u32 txq_wr_ptr:11; // bits 0-10
#else
u32 txq_wr_ptr:11; // bits 0-10
u32 reserved:5; // bits 11-15
u32 txq_rd_ptr:11; // bits 16-26
u32 reserved2:5; // bits 27-31
#endif
} bits;
} TXMAC_SHADOW_PTR_t, *PTXMAC_SHADOW_PTR_t;
/*
* structure for error count reg in txmac address map
* located at address 0x3008
*/
typedef union _TXMAC_ERR_CNT_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:20; // bits 12-31
u32 reserved:4; // bits 8-11
u32 txq_underrun:4; // bits 4-7
u32 fifo_underrun:4; // bits 0-3
#else
u32 fifo_underrun:4; // bits 0-3
u32 txq_underrun:4; // bits 4-7
u32 reserved:4; // bits 8-11
u32 unused:20; // bits 12-31
#endif
} bits;
} TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
/*
* structure for max fill reg in txmac address map
* located at address 0x300C
*/
typedef union _TXMAC_MAX_FILL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:20; // bits 12-31
u32 max_fill:12; // bits 0-11
#else
u32 max_fill:12; // bits 0-11
u32 unused:20; // bits 12-31
#endif
} bits;
} TXMAC_MAX_FILL_t, *PTXMAC_MAX_FILL_t;
/*
* structure for cf parameter reg in txmac address map
* located at address 0x3010
*/
typedef union _TXMAC_CF_PARAM_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 cfep:16; // bits 16-31
u32 cfpt:16; // bits 0-15
#else
u32 cfpt:16; // bits 0-15
u32 cfep:16; // bits 16-31
#endif
} bits;
} TXMAC_CF_PARAM_t, *PTXMAC_CF_PARAM_t;
/*
* structure for tx test reg in txmac address map
* located at address 0x3014
*/
typedef union _TXMAC_TXTEST_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused2:15; // bits 17-31
u32 reserved1:1; // bit 16
u32 txtest_en:1; // bit 15
u32 unused1:4; // bits 11-14
u32 txqtest_ptr:11; // bits 0-11
#else
u32 txqtest_ptr:11; // bits 0-10
u32 unused1:4; // bits 11-14
u32 txtest_en:1; // bit 15
u32 reserved1:1; // bit 16
u32 unused2:15; // bits 17-31
#endif
} bits;
} TXMAC_TXTEST_t, *PTXMAC_TXTEST_t;
/*
* structure for error reg in txmac address map
* located at address 0x3018
*/
typedef union _TXMAC_ERR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused2:23; // bits 9-31
u32 fifo_underrun:1; // bit 8
u32 unused1:2; // bits 6-7
u32 ctrl2_err:1; // bit 5
u32 txq_underrun:1; // bit 4
u32 bcnt_err:1; // bit 3
u32 lseg_err:1; // bit 2
u32 segnum_err:1; // bit 1
u32 seg0_err:1; // bit 0
#else
u32 seg0_err:1; // bit 0
u32 segnum_err:1; // bit 1
u32 lseg_err:1; // bit 2
u32 bcnt_err:1; // bit 3
u32 txq_underrun:1; // bit 4
u32 ctrl2_err:1; // bit 5
u32 unused1:2; // bits 6-7
u32 fifo_underrun:1; // bit 8
u32 unused2:23; // bits 9-31
#endif
} bits;
} TXMAC_ERR_t, *PTXMAC_ERR_t;
/*
* structure for error interrupt reg in txmac address map
* located at address 0x301C
*/
typedef union _TXMAC_ERR_INT_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused2:23; // bits 9-31
u32 fifo_underrun:1; // bit 8
u32 unused1:2; // bits 6-7
u32 ctrl2_err:1; // bit 5
u32 txq_underrun:1; // bit 4
u32 bcnt_err:1; // bit 3
u32 lseg_err:1; // bit 2
u32 segnum_err:1; // bit 1
u32 seg0_err:1; // bit 0
#else
u32 seg0_err:1; // bit 0
u32 segnum_err:1; // bit 1
u32 lseg_err:1; // bit 2
u32 bcnt_err:1; // bit 3
u32 txq_underrun:1; // bit 4
u32 ctrl2_err:1; // bit 5
u32 unused1:2; // bits 6-7
u32 fifo_underrun:1; // bit 8
u32 unused2:23; // bits 9-31
#endif
} bits;
} TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
/*
* structure for error interrupt reg in txmac address map
* located at address 0x3020
*/
typedef union _TXMAC_CP_CTRL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:30; // bits 2-31
u32 bp_req:1; // bit 1
u32 bp_xonxoff:1; // bit 0
#else
u32 bp_xonxoff:1; // bit 0
u32 bp_req:1; // bit 1
u32 unused:30; // bits 2-31
#endif
} bits;
} TXMAC_BP_CTRL_t, *PTXMAC_BP_CTRL_t;
/*
* Tx MAC Module of JAGCore Address Mapping
*/
typedef struct _TXMAC_t { // Location:
TXMAC_CTL_t ctl; // 0x3000
TXMAC_SHADOW_PTR_t shadow_ptr; // 0x3004
TXMAC_ERR_CNT_t err_cnt; // 0x3008
TXMAC_MAX_FILL_t max_fill; // 0x300C
TXMAC_CF_PARAM_t cf_param; // 0x3010
TXMAC_TXTEST_t tx_test; // 0x3014
TXMAC_ERR_t err; // 0x3018
TXMAC_ERR_INT_t err_int; // 0x301C
TXMAC_BP_CTRL_t bp_ctrl; // 0x3020
} TXMAC_t, *PTXMAC_t;
/* END OF TXMAC REGISTER ADDRESS MAP */
/* START OF RXMAC REGISTER ADDRESS MAP */
/*
* structure for rxmac control reg in rxmac address map
* located at address 0x4000
*/
typedef union _RXMAC_CTRL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:25; // bits 7-31
u32 rxmac_int_disable:1; // bit 6
u32 async_disable:1; // bit 5
u32 mif_disable:1; // bit 4
u32 wol_disable:1; // bit 3
u32 pkt_filter_disable:1; // bit 2
u32 mcif_disable:1; // bit 1
u32 rxmac_en:1; // bit 0
#else
u32 rxmac_en:1; // bit 0
u32 mcif_disable:1; // bit 1
u32 pkt_filter_disable:1; // bit 2
u32 wol_disable:1; // bit 3
u32 mif_disable:1; // bit 4
u32 async_disable:1; // bit 5
u32 rxmac_int_disable:1; // bit 6
u32 reserved:25; // bits 7-31
#endif
} bits;
} RXMAC_CTRL_t, *PRXMAC_CTRL_t;
/*
* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
* located at address 0x4004
*/
typedef union _RXMAC_WOL_CTL_CRC0_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 crc0:16; // bits 16-31
u32 reserve:4; // bits 12-15
u32 ignore_pp:1; // bit 11
u32 ignore_mp:1; // bit 10
u32 clr_intr:1; // bit 9
u32 ignore_link_chg:1; // bit 8
u32 ignore_uni:1; // bit 7
u32 ignore_multi:1; // bit 6
u32 ignore_broad:1; // bit 5
u32 valid_crc4:1; // bit 4
u32 valid_crc3:1; // bit 3
u32 valid_crc2:1; // bit 2
u32 valid_crc1:1; // bit 1
u32 valid_crc0:1; // bit 0
#else
u32 valid_crc0:1; // bit 0
u32 valid_crc1:1; // bit 1
u32 valid_crc2:1; // bit 2
u32 valid_crc3:1; // bit 3
u32 valid_crc4:1; // bit 4
u32 ignore_broad:1; // bit 5
u32 ignore_multi:1; // bit 6
u32 ignore_uni:1; // bit 7
u32 ignore_link_chg:1; // bit 8
u32 clr_intr:1; // bit 9
u32 ignore_mp:1; // bit 10
u32 ignore_pp:1; // bit 11
u32 reserve:4; // bits 12-15
u32 crc0:16; // bits 16-31
#endif
} bits;
} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
/*
* structure for CRC 1 and CRC 2 reg in rxmac address map
* located at address 0x4008
*/
typedef union _RXMAC_WOL_CRC12_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 crc2:16; // bits 16-31
u32 crc1:16; // bits 0-15
#else
u32 crc1:16; // bits 0-15
u32 crc2:16; // bits 16-31
#endif
} bits;
} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
/*
* structure for CRC 3 and CRC 4 reg in rxmac address map
* located at address 0x400C
*/
typedef union _RXMAC_WOL_CRC34_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 crc4:16; // bits 16-31
u32 crc3:16; // bits 0-15
#else
u32 crc3:16; // bits 0-15
u32 crc4:16; // bits 16-31
#endif
} bits;
} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
/*
* structure for Wake On Lan Source Address Lo reg in rxmac address map
* located at address 0x4010
*/
typedef union _RXMAC_WOL_SA_LO_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 sa3:8; // bits 24-31
u32 sa4:8; // bits 16-23
u32 sa5:8; // bits 8-15
u32 sa6:8; // bits 0-7
#else
u32 sa6:8; // bits 0-7
u32 sa5:8; // bits 8-15
u32 sa4:8; // bits 16-23
u32 sa3:8; // bits 24-31
#endif
} bits;
} RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
/*
* structure for Wake On Lan Source Address Hi reg in rxmac address map
* located at address 0x4014
*/
typedef union _RXMAC_WOL_SA_HI_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:16; // bits 16-31
u32 sa1:8; // bits 8-15
u32 sa2:8; // bits 0-7
#else
u32 sa2:8; // bits 0-7
u32 sa1:8; // bits 8-15
u32 reserved:16; // bits 16-31
#endif
} bits;
} RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
/*
* structure for Wake On Lan mask reg in rxmac address map
* located at address 0x4018 - 0x4064
* Defined earlier (u32)
*/
/*
* structure for Unicast Paket Filter Address 1 reg in rxmac address map
* located at address 0x4068
*/
typedef union _RXMAC_UNI_PF_ADDR1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 addr1_3:8; // bits 24-31
u32 addr1_4:8; // bits 16-23
u32 addr1_5:8; // bits 8-15
u32 addr1_6:8; // bits 0-7
#else
u32 addr1_6:8; // bits 0-7
u32 addr1_5:8; // bits 8-15
u32 addr1_4:8; // bits 16-23
u32 addr1_3:8; // bits 24-31
#endif
} bits;
} RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
/*
* structure for Unicast Paket Filter Address 2 reg in rxmac address map
* located at address 0x406C
*/
typedef union _RXMAC_UNI_PF_ADDR2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 addr2_3:8; // bits 24-31
u32 addr2_4:8; // bits 16-23
u32 addr2_5:8; // bits 8-15
u32 addr2_6:8; // bits 0-7
#else
u32 addr2_6:8; // bits 0-7
u32 addr2_5:8; // bits 8-15
u32 addr2_4:8; // bits 16-23
u32 addr2_3:8; // bits 24-31
#endif
} bits;
} RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
/*
* structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
* located at address 0x4070
*/
typedef union _RXMAC_UNI_PF_ADDR3_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 addr2_1:8; // bits 24-31
u32 addr2_2:8; // bits 16-23
u32 addr1_1:8; // bits 8-15
u32 addr1_2:8; // bits 0-7
#else
u32 addr1_2:8; // bits 0-7
u32 addr1_1:8; // bits 8-15
u32 addr2_2:8; // bits 16-23
u32 addr2_1:8; // bits 24-31
#endif
} bits;
} RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
/*
* structure for Multicast Hash reg in rxmac address map
* located at address 0x4074 - 0x4080
* Defined earlier (u32)
*/
/*
* structure for Packet Filter Control reg in rxmac address map
* located at address 0x4084
*/
typedef union _RXMAC_PF_CTRL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused2:9; // bits 23-31
u32 min_pkt_size:7; // bits 16-22
u32 unused1:12; // bits 4-15
u32 filter_frag_en:1; // bit 3
u32 filter_uni_en:1; // bit 2
u32 filter_multi_en:1; // bit 1
u32 filter_broad_en:1; // bit 0
#else
u32 filter_broad_en:1; // bit 0
u32 filter_multi_en:1; // bit 1
u32 filter_uni_en:1; // bit 2
u32 filter_frag_en:1; // bit 3
u32 unused1:12; // bits 4-15
u32 min_pkt_size:7; // bits 16-22
u32 unused2:9; // bits 23-31
#endif
} bits;
} RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
/*
* structure for Memory Controller Interface Control Max Segment reg in rxmac
* address map. Located at address 0x4088
*/
typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:22; // bits 10-31
u32 max_size:8; // bits 2-9
u32 fc_en:1; // bit 1
u32 seg_en:1; // bit 0
#else
u32 seg_en:1; // bit 0
u32 fc_en:1; // bit 1
u32 max_size:8; // bits 2-9
u32 reserved:22; // bits 10-31
#endif
} bits;
} RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
/*
* structure for Memory Controller Interface Water Mark reg in rxmac address
* map. Located at address 0x408C
*/
typedef union _RXMAC_MCIF_WATER_MARK_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved2:6; // bits 26-31
u32 mark_hi:10; // bits 16-25
u32 reserved1:6; // bits 10-15
u32 mark_lo:10; // bits 0-9
#else
u32 mark_lo:10; // bits 0-9
u32 reserved1:6; // bits 10-15
u32 mark_hi:10; // bits 16-25
u32 reserved2:6; // bits 26-31
#endif
} bits;
} RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
/*
* structure for Rx Queue Dialog reg in rxmac address map.
* located at address 0x4090
*/
typedef union _RXMAC_RXQ_DIAG_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved2:6; // bits 26-31
u32 rd_ptr:10; // bits 16-25
u32 reserved1:6; // bits 10-15
u32 wr_ptr:10; // bits 0-9
#else
u32 wr_ptr:10; // bits 0-9
u32 reserved1:6; // bits 10-15
u32 rd_ptr:10; // bits 16-25
u32 reserved2:6; // bits 26-31
#endif
} bits;
} RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
/*
* structure for space availiable reg in rxmac address map.
* located at address 0x4094
*/
typedef union _RXMAC_SPACE_AVAIL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved2:15; // bits 17-31
u32 space_avail_en:1; // bit 16
u32 reserved1:6; // bits 10-15
u32 space_avail:10; // bits 0-9
#else
u32 space_avail:10; // bits 0-9
u32 reserved1:6; // bits 10-15
u32 space_avail_en:1; // bit 16
u32 reserved2:15; // bits 17-31
#endif
} bits;
} RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
/*
* structure for management interface reg in rxmac address map.
* located at address 0x4098
*/
typedef union _RXMAC_MIF_CTL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserve:14; // bits 18-31
u32 drop_pkt_en:1; // bit 17
u32 drop_pkt_mask:17; // bits 0-16
#else
u32 drop_pkt_mask:17; // bits 0-16
u32 drop_pkt_en:1; // bit 17
u32 reserve:14; // bits 18-31
#endif
} bits;
} RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
/*
* structure for Error reg in rxmac address map.
* located at address 0x409C
*/
typedef union _RXMAC_ERROR_REG_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserve:28; // bits 4-31
u32 mif:1; // bit 3
u32 async:1; // bit 2
u32 pkt_filter:1; // bit 1
u32 mcif:1; // bit 0
#else
u32 mcif:1; // bit 0
u32 pkt_filter:1; // bit 1
u32 async:1; // bit 2
u32 mif:1; // bit 3
u32 reserve:28; // bits 4-31
#endif
} bits;
} RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
/*
* Rx MAC Module of JAGCore Address Mapping
*/
typedef struct _RXMAC_t { // Location:
RXMAC_CTRL_t ctrl; // 0x4000
RXMAC_WOL_CTL_CRC0_t crc0; // 0x4004
RXMAC_WOL_CRC12_t crc12; // 0x4008
RXMAC_WOL_CRC34_t crc34; // 0x400C
RXMAC_WOL_SA_LO_t sa_lo; // 0x4010
RXMAC_WOL_SA_HI_t sa_hi; // 0x4014
u32 mask0_word0; // 0x4018
u32 mask0_word1; // 0x401C
u32 mask0_word2; // 0x4020
u32 mask0_word3; // 0x4024
u32 mask1_word0; // 0x4028
u32 mask1_word1; // 0x402C
u32 mask1_word2; // 0x4030
u32 mask1_word3; // 0x4034
u32 mask2_word0; // 0x4038
u32 mask2_word1; // 0x403C
u32 mask2_word2; // 0x4040
u32 mask2_word3; // 0x4044
u32 mask3_word0; // 0x4048
u32 mask3_word1; // 0x404C
u32 mask3_word2; // 0x4050
u32 mask3_word3; // 0x4054
u32 mask4_word0; // 0x4058
u32 mask4_word1; // 0x405C
u32 mask4_word2; // 0x4060
u32 mask4_word3; // 0x4064
RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; // 0x4068
RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; // 0x406C
RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; // 0x4070
u32 multi_hash1; // 0x4074
u32 multi_hash2; // 0x4078
u32 multi_hash3; // 0x407C
u32 multi_hash4; // 0x4080
RXMAC_PF_CTRL_t pf_ctrl; // 0x4084
RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; // 0x4088
RXMAC_MCIF_WATER_MARK_t mcif_water_mark; // 0x408C
RXMAC_RXQ_DIAG_t rxq_diag; // 0x4090
RXMAC_SPACE_AVAIL_t space_avail; // 0x4094
RXMAC_MIF_CTL_t mif_ctrl; // 0x4098
RXMAC_ERROR_REG_t err_reg; // 0x409C
} RXMAC_t, *PRXMAC_t;
/* END OF TXMAC REGISTER ADDRESS MAP */
/* START OF MAC REGISTER ADDRESS MAP */
/*
* structure for configuration #1 reg in mac address map.
* located at address 0x5000
*/
typedef union _MAC_CFG1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 soft_reset:1; // bit 31
u32 sim_reset:1; // bit 30
u32 reserved3:10; // bits 20-29
u32 reset_rx_mc:1; // bit 19
u32 reset_tx_mc:1; // bit 18
u32 reset_rx_fun:1; // bit 17
u32 reset_tx_fun:1; // bit 16
u32 reserved2:7; // bits 9-15
u32 loop_back:1; // bit 8
u32 reserved1:2; // bits 6-7
u32 rx_flow:1; // bit 5
u32 tx_flow:1; // bit 4
u32 syncd_rx_en:1; // bit 3
u32 rx_enable:1; // bit 2
u32 syncd_tx_en:1; // bit 1
u32 tx_enable:1; // bit 0
#else
u32 tx_enable:1; // bit 0
u32 syncd_tx_en:1; // bit 1
u32 rx_enable:1; // bit 2
u32 syncd_rx_en:1; // bit 3
u32 tx_flow:1; // bit 4
u32 rx_flow:1; // bit 5
u32 reserved1:2; // bits 6-7
u32 loop_back:1; // bit 8
u32 reserved2:7; // bits 9-15
u32 reset_tx_fun:1; // bit 16
u32 reset_rx_fun:1; // bit 17
u32 reset_tx_mc:1; // bit 18
u32 reset_rx_mc:1; // bit 19
u32 reserved3:10; // bits 20-29
u32 sim_reset:1; // bit 30
u32 soft_reset:1; // bit 31
#endif
} bits;
} MAC_CFG1_t, *PMAC_CFG1_t;
/*
* structure for configuration #2 reg in mac address map.
* located at address 0x5004
*/
typedef union _MAC_CFG2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved3:16; // bits 16-31
u32 preamble_len:4; // bits 12-15
u32 reserved2:2; // bits 10-11
u32 if_mode:2; // bits 8-9
u32 reserved1:2; // bits 6-7
u32 huge_frame:1; // bit 5
u32 len_check:1; // bit 4
u32 undefined:1; // bit 3
u32 pad_crc:1; // bit 2
u32 crc_enable:1; // bit 1
u32 full_duplex:1; // bit 0
#else
u32 full_duplex:1; // bit 0
u32 crc_enable:1; // bit 1
u32 pad_crc:1; // bit 2
u32 undefined:1; // bit 3
u32 len_check:1; // bit 4
u32 huge_frame:1; // bit 5
u32 reserved1:2; // bits 6-7
u32 if_mode:2; // bits 8-9
u32 reserved2:2; // bits 10-11
u32 preamble_len:4; // bits 12-15
u32 reserved3:16; // bits 16-31
#endif
} bits;
} MAC_CFG2_t, *PMAC_CFG2_t;
/*
* structure for Interpacket gap reg in mac address map.
* located at address 0x5008
*/
typedef union _MAC_IPG_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:1; // bit 31
u32 non_B2B_ipg_1:7; // bits 24-30
u32 undefined2:1; // bit 23
u32 non_B2B_ipg_2:7; // bits 16-22
u32 min_ifg_enforce:8; // bits 8-15
u32 undefined1:1; // bit 7
u32 B2B_ipg:7; // bits 0-6
#else
u32 B2B_ipg:7; // bits 0-6
u32 undefined1:1; // bit 7
u32 min_ifg_enforce:8; // bits 8-15
u32 non_B2B_ipg_2:7; // bits 16-22
u32 undefined2:1; // bit 23
u32 non_B2B_ipg_1:7; // bits 24-30
u32 reserved:1; // bit 31
#endif
} bits;
} MAC_IPG_t, *PMAC_IPG_t;
/*
* structure for half duplex reg in mac address map.
* located at address 0x500C
*/
typedef union _MAC_HFDP_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved2:8; // bits 24-31
u32 alt_beb_trunc:4; // bits 23-20
u32 alt_beb_enable:1; // bit 19
u32 bp_no_backoff:1; // bit 18
u32 no_backoff:1; // bit 17
u32 excess_defer:1; // bit 16
u32 rexmit_max:4; // bits 12-15
u32 reserved1:2; // bits 10-11
u32 coll_window:10; // bits 0-9
#else
u32 coll_window:10; // bits 0-9
u32 reserved1:2; // bits 10-11
u32 rexmit_max:4; // bits 12-15
u32 excess_defer:1; // bit 16
u32 no_backoff:1; // bit 17
u32 bp_no_backoff:1; // bit 18
u32 alt_beb_enable:1; // bit 19
u32 alt_beb_trunc:4; // bits 23-20
u32 reserved2:8; // bits 24-31
#endif
} bits;
} MAC_HFDP_t, *PMAC_HFDP_t;
/*
* structure for Maximum Frame Length reg in mac address map.
* located at address 0x5010
*/
typedef union _MAC_MAX_FM_LEN_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:16; // bits 16-31
u32 max_len:16; // bits 0-15
#else
u32 max_len:16; // bits 0-15
u32 reserved:16; // bits 16-31
#endif
} bits;
} MAC_MAX_FM_LEN_t, *PMAC_MAX_FM_LEN_t;
/*
* structure for Reserve 1 reg in mac address map.
* located at address 0x5014 - 0x5018
* Defined earlier (u32)
*/
/*
* structure for Test reg in mac address map.
* located at address 0x501C
*/
typedef union _MAC_TEST_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:29; // bits 3-31
u32 mac_test:3; // bits 0-2
#else
u32 mac_test:3; // bits 0-2
u32 unused:29; // bits 3-31
#endif
} bits;
} MAC_TEST_t, *PMAC_TEST_t;
/*
* structure for MII Management Configuration reg in mac address map.
* located at address 0x5020
*/
typedef union _MII_MGMT_CFG_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reset_mii_mgmt:1; // bit 31
u32 reserved:25; // bits 6-30
u32 scan_auto_incremt:1; // bit 5
u32 preamble_suppress:1; // bit 4
u32 undefined:1; // bit 3
u32 mgmt_clk_reset:3; // bits 0-2
#else
u32 mgmt_clk_reset:3; // bits 0-2
u32 undefined:1; // bit 3
u32 preamble_suppress:1; // bit 4
u32 scan_auto_incremt:1; // bit 5
u32 reserved:25; // bits 6-30
u32 reset_mii_mgmt:1; // bit 31
#endif
} bits;
} MII_MGMT_CFG_t, *PMII_MGMT_CFG_t;
/*
* structure for MII Management Command reg in mac address map.
* located at address 0x5024
*/
typedef union _MII_MGMT_CMD_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:30; // bits 2-31
u32 scan_cycle:1; // bit 1
u32 read_cycle:1; // bit 0
#else
u32 read_cycle:1; // bit 0
u32 scan_cycle:1; // bit 1
u32 reserved:30; // bits 2-31
#endif
} bits;
} MII_MGMT_CMD_t, *PMII_MGMT_CMD_t;
/*
* structure for MII Management Address reg in mac address map.
* located at address 0x5028
*/
typedef union _MII_MGMT_ADDR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved2:19; // bit 13-31
u32 phy_addr:5; // bits 8-12
u32 reserved1:3; // bits 5-7
u32 reg_addr:5; // bits 0-4
#else
u32 reg_addr:5; // bits 0-4
u32 reserved1:3; // bits 5-7
u32 phy_addr:5; // bits 8-12
u32 reserved2:19; // bit 13-31
#endif
} bits;
} MII_MGMT_ADDR_t, *PMII_MGMT_ADDR_t;
/*
* structure for MII Management Control reg in mac address map.
* located at address 0x502C
*/
typedef union _MII_MGMT_CTRL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:16; // bits 16-31
u32 phy_ctrl:16; // bits 0-15
#else
u32 phy_ctrl:16; // bits 0-15
u32 reserved:16; // bits 16-31
#endif
} bits;
} MII_MGMT_CTRL_t, *PMII_MGMT_CTRL_t;
/*
* structure for MII Management Status reg in mac address map.
* located at address 0x5030
*/
typedef union _MII_MGMT_STAT_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:16; // bits 16-31
u32 phy_stat:16; // bits 0-15
#else
u32 phy_stat:16; // bits 0-15
u32 reserved:16; // bits 16-31
#endif
} bits;
} MII_MGMT_STAT_t, *PMII_MGMT_STAT_t;
/*
* structure for MII Management Indicators reg in mac address map.
* located at address 0x5034
*/
typedef union _MII_MGMT_INDICATOR_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:29; // bits 3-31
u32 not_valid:1; // bit 2
u32 scanning:1; // bit 1
u32 busy:1; // bit 0
#else
u32 busy:1; // bit 0
u32 scanning:1; // bit 1
u32 not_valid:1; // bit 2
u32 reserved:29; // bits 3-31
#endif
} bits;
} MII_MGMT_INDICATOR_t, *PMII_MGMT_INDICATOR_t;
/*
* structure for Interface Control reg in mac address map.
* located at address 0x5038
*/
typedef union _MAC_IF_CTRL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reset_if_module:1; // bit 31
u32 reserved4:3; // bit 28-30
u32 tbi_mode:1; // bit 27
u32 ghd_mode:1; // bit 26
u32 lhd_mode:1; // bit 25
u32 phy_mode:1; // bit 24
u32 reset_per_mii:1; // bit 23
u32 reserved3:6; // bits 17-22
u32 speed:1; // bit 16
u32 reset_pe100x:1; // bit 15
u32 reserved2:4; // bits 11-14
u32 force_quiet:1; // bit 10
u32 no_cipher:1; // bit 9
u32 disable_link_fail:1; // bit 8
u32 reset_gpsi:1; // bit 7
u32 reserved1:6; // bits 1-6
u32 enab_jab_protect:1; // bit 0
#else
u32 enab_jab_protect:1; // bit 0
u32 reserved1:6; // bits 1-6
u32 reset_gpsi:1; // bit 7
u32 disable_link_fail:1; // bit 8
u32 no_cipher:1; // bit 9
u32 force_quiet:1; // bit 10
u32 reserved2:4; // bits 11-14
u32 reset_pe100x:1; // bit 15
u32 speed:1; // bit 16
u32 reserved3:6; // bits 17-22
u32 reset_per_mii:1; // bit 23
u32 phy_mode:1; // bit 24
u32 lhd_mode:1; // bit 25
u32 ghd_mode:1; // bit 26
u32 tbi_mode:1; // bit 27
u32 reserved4:3; // bit 28-30
u32 reset_if_module:1; // bit 31
#endif
} bits;
} MAC_IF_CTRL_t, *PMAC_IF_CTRL_t;
/*
* structure for Interface Status reg in mac address map.
* located at address 0x503C
*/
typedef union _MAC_IF_STAT_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:22; // bits 10-31
u32 excess_defer:1; // bit 9
u32 clash:1; // bit 8
u32 phy_jabber:1; // bit 7
u32 phy_link_ok:1; // bit 6
u32 phy_full_duplex:1; // bit 5
u32 phy_speed:1; // bit 4
u32 pe100x_link_fail:1; // bit 3
u32 pe10t_loss_carrie:1; // bit 2
u32 pe10t_sqe_error:1; // bit 1
u32 pe10t_jabber:1; // bit 0
#else
u32 pe10t_jabber:1; // bit 0
u32 pe10t_sqe_error:1; // bit 1
u32 pe10t_loss_carrie:1; // bit 2
u32 pe100x_link_fail:1; // bit 3
u32 phy_speed:1; // bit 4
u32 phy_full_duplex:1; // bit 5
u32 phy_link_ok:1; // bit 6
u32 phy_jabber:1; // bit 7
u32 clash:1; // bit 8
u32 excess_defer:1; // bit 9
u32 reserved:22; // bits 10-31
#endif
} bits;
} MAC_IF_STAT_t, *PMAC_IF_STAT_t;
/*
* structure for Mac Station Address, Part 1 reg in mac address map.
* located at address 0x5040
*/
typedef union _MAC_STATION_ADDR1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 Octet6:8; // bits 24-31
u32 Octet5:8; // bits 16-23
u32 Octet4:8; // bits 8-15
u32 Octet3:8; // bits 0-7
#else
u32 Octet3:8; // bits 0-7
u32 Octet4:8; // bits 8-15
u32 Octet5:8; // bits 16-23
u32 Octet6:8; // bits 24-31
#endif
} bits;
} MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
/*
* structure for Mac Station Address, Part 2 reg in mac address map.
* located at address 0x5044
*/
typedef union _MAC_STATION_ADDR2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 Octet2:8; // bits 24-31
u32 Octet1:8; // bits 16-23
u32 reserved:16; // bits 0-15
#else
u32 reserved:16; // bit 0-15
u32 Octet1:8; // bits 16-23
u32 Octet2:8; // bits 24-31
#endif
} bits;
} MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
/*
* MAC Module of JAGCore Address Mapping
*/
typedef struct _MAC_t { // Location:
MAC_CFG1_t cfg1; // 0x5000
MAC_CFG2_t cfg2; // 0x5004
MAC_IPG_t ipg; // 0x5008
MAC_HFDP_t hfdp; // 0x500C
MAC_MAX_FM_LEN_t max_fm_len; // 0x5010
u32 rsv1; // 0x5014
u32 rsv2; // 0x5018
MAC_TEST_t mac_test; // 0x501C
MII_MGMT_CFG_t mii_mgmt_cfg; // 0x5020
MII_MGMT_CMD_t mii_mgmt_cmd; // 0x5024
MII_MGMT_ADDR_t mii_mgmt_addr; // 0x5028
MII_MGMT_CTRL_t mii_mgmt_ctrl; // 0x502C
MII_MGMT_STAT_t mii_mgmt_stat; // 0x5030
MII_MGMT_INDICATOR_t mii_mgmt_indicator; // 0x5034
MAC_IF_CTRL_t if_ctrl; // 0x5038
MAC_IF_STAT_t if_stat; // 0x503C
MAC_STATION_ADDR1_t station_addr_1; // 0x5040
MAC_STATION_ADDR2_t station_addr_2; // 0x5044
} MAC_t, *PMAC_t;
/* END OF MAC REGISTER ADDRESS MAP */
/* START OF MAC STAT REGISTER ADDRESS MAP */
/*
* structure for Carry Register One and it's Mask Register reg located in mac
* stat address map address 0x6130 and 0x6138.
*/
typedef union _MAC_STAT_REG_1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 tr64:1; // bit 31
u32 tr127:1; // bit 30
u32 tr255:1; // bit 29
u32 tr511:1; // bit 28
u32 tr1k:1; // bit 27
u32 trmax:1; // bit 26
u32 trmgv:1; // bit 25
u32 unused:8; // bits 17-24
u32 rbyt:1; // bit 16
u32 rpkt:1; // bit 15
u32 rfcs:1; // bit 14
u32 rmca:1; // bit 13
u32 rbca:1; // bit 12
u32 rxcf:1; // bit 11
u32 rxpf:1; // bit 10
u32 rxuo:1; // bit 9
u32 raln:1; // bit 8
u32 rflr:1; // bit 7
u32 rcde:1; // bit 6
u32 rcse:1; // bit 5
u32 rund:1; // bit 4
u32 rovr:1; // bit 3
u32 rfrg:1; // bit 2
u32 rjbr:1; // bit 1
u32 rdrp:1; // bit 0
#else
u32 rdrp:1; // bit 0
u32 rjbr:1; // bit 1
u32 rfrg:1; // bit 2
u32 rovr:1; // bit 3
u32 rund:1; // bit 4
u32 rcse:1; // bit 5
u32 rcde:1; // bit 6
u32 rflr:1; // bit 7
u32 raln:1; // bit 8
u32 rxuo:1; // bit 9
u32 rxpf:1; // bit 10
u32 rxcf:1; // bit 11
u32 rbca:1; // bit 12
u32 rmca:1; // bit 13
u32 rfcs:1; // bit 14
u32 rpkt:1; // bit 15
u32 rbyt:1; // bit 16
u32 unused:8; // bits 17-24
u32 trmgv:1; // bit 25
u32 trmax:1; // bit 26
u32 tr1k:1; // bit 27
u32 tr511:1; // bit 28
u32 tr255:1; // bit 29
u32 tr127:1; // bit 30
u32 tr64:1; // bit 31
#endif
} bits;
} MAC_STAT_REG_1_t, *PMAC_STAT_REG_1_t;
/*
* structure for Carry Register Two Mask Register reg in mac stat address map.
* located at address 0x613C
*/
typedef union _MAC_STAT_REG_2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:12; // bit 20-31
u32 tjbr:1; // bit 19
u32 tfcs:1; // bit 18
u32 txcf:1; // bit 17
u32 tovr:1; // bit 16
u32 tund:1; // bit 15
u32 tfrg:1; // bit 14
u32 tbyt:1; // bit 13
u32 tpkt:1; // bit 12
u32 tmca:1; // bit 11
u32 tbca:1; // bit 10
u32 txpf:1; // bit 9
u32 tdfr:1; // bit 8
u32 tedf:1; // bit 7
u32 tscl:1; // bit 6
u32 tmcl:1; // bit 5
u32 tlcl:1; // bit 4
u32 txcl:1; // bit 3
u32 tncl:1; // bit 2
u32 tpfh:1; // bit 1
u32 tdrp:1; // bit 0
#else
u32 tdrp:1; // bit 0
u32 tpfh:1; // bit 1
u32 tncl:1; // bit 2
u32 txcl:1; // bit 3
u32 tlcl:1; // bit 4
u32 tmcl:1; // bit 5
u32 tscl:1; // bit 6
u32 tedf:1; // bit 7
u32 tdfr:1; // bit 8
u32 txpf:1; // bit 9
u32 tbca:1; // bit 10
u32 tmca:1; // bit 11
u32 tpkt:1; // bit 12
u32 tbyt:1; // bit 13
u32 tfrg:1; // bit 14
u32 tund:1; // bit 15
u32 tovr:1; // bit 16
u32 txcf:1; // bit 17
u32 tfcs:1; // bit 18
u32 tjbr:1; // bit 19
u32 unused:12; // bit 20-31
#endif
} bits;
} MAC_STAT_REG_2_t, *PMAC_STAT_REG_2_t;
/*
* MAC STATS Module of JAGCore Address Mapping
*/
typedef struct _MAC_STAT_t { // Location:
u32 pad[32]; // 0x6000 - 607C
// Tx/Rx 0-64 Byte Frame Counter
u32 TR64; // 0x6080
// Tx/Rx 65-127 Byte Frame Counter
u32 TR127; // 0x6084
// Tx/Rx 128-255 Byte Frame Counter
u32 TR255; // 0x6088
// Tx/Rx 256-511 Byte Frame Counter
u32 TR511; // 0x608C
// Tx/Rx 512-1023 Byte Frame Counter
u32 TR1K; // 0x6090
// Tx/Rx 1024-1518 Byte Frame Counter
u32 TRMax; // 0x6094
// Tx/Rx 1519-1522 Byte Good VLAN Frame Count
u32 TRMgv; // 0x6098
// Rx Byte Counter
u32 RByt; // 0x609C
// Rx Packet Counter
u32 RPkt; // 0x60A0
// Rx FCS Error Counter
u32 RFcs; // 0x60A4
// Rx Multicast Packet Counter
u32 RMca; // 0x60A8
// Rx Broadcast Packet Counter
u32 RBca; // 0x60AC
// Rx Control Frame Packet Counter
u32 RxCf; // 0x60B0
// Rx Pause Frame Packet Counter
u32 RxPf; // 0x60B4
// Rx Unknown OP Code Counter
u32 RxUo; // 0x60B8
// Rx Alignment Error Counter
u32 RAln; // 0x60BC
// Rx Frame Length Error Counter
u32 RFlr; // 0x60C0
// Rx Code Error Counter
u32 RCde; // 0x60C4
// Rx Carrier Sense Error Counter
u32 RCse; // 0x60C8
// Rx Undersize Packet Counter
u32 RUnd; // 0x60CC
// Rx Oversize Packet Counter
u32 ROvr; // 0x60D0
// Rx Fragment Counter
u32 RFrg; // 0x60D4
// Rx Jabber Counter
u32 RJbr; // 0x60D8
// Rx Drop
u32 RDrp; // 0x60DC
// Tx Byte Counter
u32 TByt; // 0x60E0
// Tx Packet Counter
u32 TPkt; // 0x60E4
// Tx Multicast Packet Counter
u32 TMca; // 0x60E8
// Tx Broadcast Packet Counter
u32 TBca; // 0x60EC
// Tx Pause Control Frame Counter
u32 TxPf; // 0x60F0
// Tx Deferral Packet Counter
u32 TDfr; // 0x60F4
// Tx Excessive Deferral Packet Counter
u32 TEdf; // 0x60F8
// Tx Single Collision Packet Counter
u32 TScl; // 0x60FC
// Tx Multiple Collision Packet Counter
u32 TMcl; // 0x6100
// Tx Late Collision Packet Counter
u32 TLcl; // 0x6104
// Tx Excessive Collision Packet Counter
u32 TXcl; // 0x6108
// Tx Total Collision Packet Counter
u32 TNcl; // 0x610C
// Tx Pause Frame Honored Counter
u32 TPfh; // 0x6110
// Tx Drop Frame Counter
u32 TDrp; // 0x6114
// Tx Jabber Frame Counter
u32 TJbr; // 0x6118
// Tx FCS Error Counter
u32 TFcs; // 0x611C
// Tx Control Frame Counter
u32 TxCf; // 0x6120
// Tx Oversize Frame Counter
u32 TOvr; // 0x6124
// Tx Undersize Frame Counter
u32 TUnd; // 0x6128
// Tx Fragments Frame Counter
u32 TFrg; // 0x612C
// Carry Register One Register
MAC_STAT_REG_1_t Carry1; // 0x6130
// Carry Register Two Register
MAC_STAT_REG_2_t Carry2; // 0x6134
// Carry Register One Mask Register
MAC_STAT_REG_1_t Carry1M; // 0x6138
// Carry Register Two Mask Register
MAC_STAT_REG_2_t Carry2M; // 0x613C
} MAC_STAT_t, *PMAC_STAT_t;
/* END OF MAC STAT REGISTER ADDRESS MAP */
/* START OF MMC REGISTER ADDRESS MAP */
/*
* structure for Main Memory Controller Control reg in mmc address map.
* located at address 0x7000
*/
typedef union _MMC_CTRL_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:25; // bits 7-31
u32 force_ce:1; // bit 6
u32 rxdma_disable:1; // bit 5
u32 txdma_disable:1; // bit 4
u32 txmac_disable:1; // bit 3
u32 rxmac_disable:1; // bit 2
u32 arb_disable:1; // bit 1
u32 mmc_enable:1; // bit 0
#else
u32 mmc_enable:1; // bit 0
u32 arb_disable:1; // bit 1
u32 rxmac_disable:1; // bit 2
u32 txmac_disable:1; // bit 3
u32 txdma_disable:1; // bit 4
u32 rxdma_disable:1; // bit 5
u32 force_ce:1; // bit 6
u32 reserved:25; // bits 7-31
#endif
} bits;
} MMC_CTRL_t, *PMMC_CTRL_t;
/*
* structure for Main Memory Controller Host Memory Access Address reg in mmc
* address map. Located at address 0x7004
*/
typedef union _MMC_SRAM_ACCESS_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 byte_enable:16; // bits 16-31
u32 reserved2:2; // bits 14-15
u32 req_addr:10; // bits 4-13
u32 reserved1:1; // bit 3
u32 is_ctrl_word:1; // bit 2
u32 wr_access:1; // bit 1
u32 req_access:1; // bit 0
#else
u32 req_access:1; // bit 0
u32 wr_access:1; // bit 1
u32 is_ctrl_word:1; // bit 2
u32 reserved1:1; // bit 3
u32 req_addr:10; // bits 4-13
u32 reserved2:2; // bits 14-15
u32 byte_enable:16; // bits 16-31
#endif
} bits;
} MMC_SRAM_ACCESS_t, *PMMC_SRAM_ACCESS_t;
/*
* structure for Main Memory Controller Host Memory Access Data reg in mmc
* address map. Located at address 0x7008 - 0x7014
* Defined earlier (u32)
*/
/*
* Memory Control Module of JAGCore Address Mapping
*/
typedef struct _MMC_t { // Location:
MMC_CTRL_t mmc_ctrl; // 0x7000
MMC_SRAM_ACCESS_t sram_access; // 0x7004
u32 sram_word1; // 0x7008
u32 sram_word2; // 0x700C
u32 sram_word3; // 0x7010
u32 sram_word4; // 0x7014
} MMC_t, *PMMC_t;
/* END OF MMC REGISTER ADDRESS MAP */
/* START OF EXP ROM REGISTER ADDRESS MAP */
/*
* Expansion ROM Module of JAGCore Address Mapping
*/
/* Take this out until it is not empty */
#if 0
typedef struct _EXP_ROM_t {
} EXP_ROM_t, *PEXP_ROM_t;
#endif
/* END OF EXP ROM REGISTER ADDRESS MAP */
/*
* JAGCore Address Mapping
*/
typedef struct _ADDRESS_MAP_t {
GLOBAL_t global;
// unused section of global address map
u8 unused_global[4096 - sizeof(GLOBAL_t)];
TXDMA_t txdma;
// unused section of txdma address map
u8 unused_txdma[4096 - sizeof(TXDMA_t)];
RXDMA_t rxdma;
// unused section of rxdma address map
u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
TXMAC_t txmac;
// unused section of txmac address map
u8 unused_txmac[4096 - sizeof(TXMAC_t)];
RXMAC_t rxmac;
// unused section of rxmac address map
u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
MAC_t mac;
// unused section of mac address map
u8 unused_mac[4096 - sizeof(MAC_t)];
MAC_STAT_t macStat;
// unused section of mac stat address map
u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
MMC_t mmc;
// unused section of mmc address map
u8 unused_mmc[4096 - sizeof(MMC_t)];
// unused section of address map
u8 unused_[1015808];
/* Take this out until it is not empty */
#if 0
EXP_ROM_t exp_rom;
#endif
u8 unused_exp_rom[4096]; // MGS-size TBD
u8 unused__[524288]; // unused section of address map
} ADDRESS_MAP_t, *PADDRESS_MAP_t;
#endif /* _ET1310_ADDRESS_MAP_H_ */
|